Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks

Abstract

The impact of surface and grain boundary scattering on the design of multi-level interconnect networks and their latency distributions is reported. For the 18-nm technology node (year 2018), it is shown that, despite more than 4/spl times/ increase in resistivity of copper for minimum size interconnects, the increase in the number of metal levels is negligible (less than 6.7%), and interconnects that will be affected most are so short that their impact on the chip performance is inconsequential.