Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499983
S. Mazur, C. E. Jackson, G. W. Foggin
Membrane-mediated electropolishing is a new process whereby a metal substrate is anodically oxidized in de-ionized water and the metal ions migrate across a charge-selective membrane to the cathode. All metal ions removed from the substrate are plated onto the cathode. In contrast with both CMP and electrochemical mechanical polishing the substrate is never exposed to abrasives or electrolytes, no reagents are consumed, no waste is generated and no post-cleaning is required. High removal rates and planarization efficiencies are achieved with low mechanical forces.
{"title":"Membrane-mediated electropolishing of damascene copper","authors":"S. Mazur, C. E. Jackson, G. W. Foggin","doi":"10.1109/IITC.2005.1499983","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499983","url":null,"abstract":"Membrane-mediated electropolishing is a new process whereby a metal substrate is anodically oxidized in de-ionized water and the metal ions migrate across a charge-selective membrane to the cathode. All metal ions removed from the substrate are plated onto the cathode. In contrast with both CMP and electrochemical mechanical polishing the substrate is never exposed to abrasives or electrolytes, no reagents are consumed, no waste is generated and no post-cleaning is required. High removal rates and planarization efficiencies are achieved with low mechanical forces.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115725072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499971
Bing Dang, P. Joseph, M. Bakir, T. Spencer, P. Kohl, J. Meindl
We present a novel CMOS compatible approach to fabricate on-chip microfluidic cooling channels using a spin-on sacrificial polymer material at wafer level. Deep trenches (>100 /spl mu/m) etched into the backside of an IC wafer were successfully filled up by a single spin coating step with a high viscosity sacrificial polymer. A porous overcoat material allows the decomposition of the polymer to form enclosed microchannels. Through chip holes and polymer pipes are used as the inlet/outlet interconnects. Different channel array designs were described and the pressure drop was estimated for a heat flux of 100 W/cm/sup 2/ with DI water flow rate. The resulting cooling scheme offers a simple and compact solution to transfer cooling liquid directly into a GSI chip and is fully compatible with flip-chip packaging.
{"title":"Wafer-level microfluidic cooling interconnects for GSI","authors":"Bing Dang, P. Joseph, M. Bakir, T. Spencer, P. Kohl, J. Meindl","doi":"10.1109/IITC.2005.1499971","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499971","url":null,"abstract":"We present a novel CMOS compatible approach to fabricate on-chip microfluidic cooling channels using a spin-on sacrificial polymer material at wafer level. Deep trenches (>100 /spl mu/m) etched into the backside of an IC wafer were successfully filled up by a single spin coating step with a high viscosity sacrificial polymer. A porous overcoat material allows the decomposition of the polymer to form enclosed microchannels. Through chip holes and polymer pipes are used as the inlet/outlet interconnects. Different channel array designs were described and the pressure drop was estimated for a heat flux of 100 W/cm/sup 2/ with DI water flow rate. The resulting cooling scheme offers a simple and compact solution to transfer cooling liquid directly into a GSI chip and is fully compatible with flip-chip packaging.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123408125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499934
R. Hoofman, J. Michelon, P. Bancken, R. Daamen, G. Verheijden, V. Arnal, O. Hinsinger, L. Gosset, A. Humbert, W. Besling, C. Goldberg, R. Fox, L. Michaelson, C. Guedj, J. Guillaumond, V. Jousseaume, L. Arnaud, D. Gravesteijn, J. Torres, G. Passemard
The continuous downscaling of interconnect dimensions in combination with the introduction of porous low-k materials has increased the number of integration challenges tremendously. The paper focuses mainly on the impact of porous low-k dielectrics on interconnect reliability. Numerous reliability issues are induced by their porosity compared to dense low-k materials. The impact of these mechanically inferior materials on packaging is well known. However, on top of the mechanical reliability, ultra low-k materials are extremely vulnerable to processing (especially to plasmas), due to their inherent porosity. Additionally, it is difficult to deposit a continuous, thin barrier on porous low-k interfaces. The inferior properties of porous low-k materials as compared to their dense equivalents are thought to induce numerous reliability issues, which are in addition to the ones caused by the continuous downscaling of metal lines and dielectric spacings. All of this together has an enormous impact on the reliability of the end product.
{"title":"Reliability challenges accompanied with interconnect downscaling and ultra low-k dielectrics","authors":"R. Hoofman, J. Michelon, P. Bancken, R. Daamen, G. Verheijden, V. Arnal, O. Hinsinger, L. Gosset, A. Humbert, W. Besling, C. Goldberg, R. Fox, L. Michaelson, C. Guedj, J. Guillaumond, V. Jousseaume, L. Arnaud, D. Gravesteijn, J. Torres, G. Passemard","doi":"10.1109/IITC.2005.1499934","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499934","url":null,"abstract":"The continuous downscaling of interconnect dimensions in combination with the introduction of porous low-k materials has increased the number of integration challenges tremendously. The paper focuses mainly on the impact of porous low-k dielectrics on interconnect reliability. Numerous reliability issues are induced by their porosity compared to dense low-k materials. The impact of these mechanically inferior materials on packaging is well known. However, on top of the mechanical reliability, ultra low-k materials are extremely vulnerable to processing (especially to plasmas), due to their inherent porosity. Additionally, it is difficult to deposit a continuous, thin barrier on porous low-k interfaces. The inferior properties of porous low-k materials as compared to their dense equivalents are thought to induce numerous reliability issues, which are in addition to the ones caused by the continuous downscaling of metal lines and dielectric spacings. All of this together has an enormous impact on the reliability of the end product.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129240672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499968
T. Suga
SAB is a process for bonding surfaces which have been cleaned and activated by ion beam bombardment or plasma irradiation. The concept is based on the reactivity of atomically clean surfaces of solids and the formation of chemical bonds on contact between such clean and activated surfaces. The bonding procedure consists of cleaning followed by contact in ultra-high vacuum or in a certain ambient atmosphere. The highly activated surfaces enable them to bond to each other at a lower temperature than the conventional bonding process. This paper reviews the development and current status of the SAB process. A high-density bumpless interconnect for Cu electrodes (3 /spl mu/m in diameter, 10 /spl mu/m pitch) of 100,000 pieces at room temperature, and its application on the assembly of a flash memory card are demonstrated. Two new additional processes using a nano-layer adhesion and a sequential activation process are proposed for bonding of ionic materials such as SiO/sub 2/, glass and LiNbO/sub 3/.
{"title":"Low temperature interconnect technology using surface activated bonding (SAB) method","authors":"T. Suga","doi":"10.1109/IITC.2005.1499968","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499968","url":null,"abstract":"SAB is a process for bonding surfaces which have been cleaned and activated by ion beam bombardment or plasma irradiation. The concept is based on the reactivity of atomically clean surfaces of solids and the formation of chemical bonds on contact between such clean and activated surfaces. The bonding procedure consists of cleaning followed by contact in ultra-high vacuum or in a certain ambient atmosphere. The highly activated surfaces enable them to bond to each other at a lower temperature than the conventional bonding process. This paper reviews the development and current status of the SAB process. A high-density bumpless interconnect for Cu electrodes (3 /spl mu/m in diameter, 10 /spl mu/m pitch) of 100,000 pieces at room temperature, and its application on the assembly of a flash memory card are demonstrated. Two new additional processes using a nano-layer adhesion and a sequential activation process are proposed for bonding of ionic materials such as SiO/sub 2/, glass and LiNbO/sub 3/.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127047859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499923
V. Jousseaume, M. Assous, A. Zenasni, S. Maitrejean, B. Remiat, P. Leduc, H. Trouvé, C. Le Cornec, M. Fayolle, A. Roule, F. Ciaramella, D. Bouchu, T. David, A. Roman, D. Scevola, T. Morel, D. Rébiscoul, G. Prokopowicz, M. Jackman, C. Guedj, D. Louis, M. Gallagher, G. Passemard
Conventional Cu-ULK integration schemes lead to a drastic increase of the dielectric constant due to porous material degradation during process steps. In this paper, a post-integration porogen removal approach is studied to overcome this issue. Material optimization is presented (k=2.0) allowing the use of conventional BEOL integration processes such as oxygen-based etch chemistry, metal CVD barrier deposition and standard CMP process for dense low k. An integrated k value lower than 2.2 is obtained.
{"title":"Cu/ULK (k=2.0) integration for 45 nm node and below using an improved hybrid material with conventional BEOL processing and a late porogen removal","authors":"V. Jousseaume, M. Assous, A. Zenasni, S. Maitrejean, B. Remiat, P. Leduc, H. Trouvé, C. Le Cornec, M. Fayolle, A. Roule, F. Ciaramella, D. Bouchu, T. David, A. Roman, D. Scevola, T. Morel, D. Rébiscoul, G. Prokopowicz, M. Jackman, C. Guedj, D. Louis, M. Gallagher, G. Passemard","doi":"10.1109/IITC.2005.1499923","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499923","url":null,"abstract":"Conventional Cu-ULK integration schemes lead to a drastic increase of the dielectric constant due to porous material degradation during process steps. In this paper, a post-integration porogen removal approach is studied to overcome this issue. Material optimization is presented (k=2.0) allowing the use of conventional BEOL integration processes such as oxygen-based etch chemistry, metal CVD barrier deposition and standard CMP process for dense low k. An integrated k value lower than 2.2 is obtained.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129176210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499952
C. Patel, P. Andry, K. Jenkins, B. Dang, R. Horton, R. Polastre, C. Tsang
Electrical characterization results of fine pitch flip chip interconnections, called microjoins, using a silicon carrier are reported. Microjoins with 50 /spl mu/m diameter, 100 /spl mu/m pitch are assembled onto a silicon carrier and characterized up to 40 GHz using transmission line test macros. Time and frequency domain measurements of a single 50 /spl mu/m diameter microjoin give 6 ps delay and less than -0.5 dB transmission losses up to 40 GHz.
{"title":"Characterization of flip chip microjoins up to 40 GHz using silicon carrier","authors":"C. Patel, P. Andry, K. Jenkins, B. Dang, R. Horton, R. Polastre, C. Tsang","doi":"10.1109/IITC.2005.1499952","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499952","url":null,"abstract":"Electrical characterization results of fine pitch flip chip interconnections, called microjoins, using a silicon carrier are reported. Microjoins with 50 /spl mu/m diameter, 100 /spl mu/m pitch are assembled onto a silicon carrier and characterized up to 40 GHz using transmission line test macros. Time and frequency domain measurements of a single 50 /spl mu/m diameter microjoin give 6 ps delay and less than -0.5 dB transmission losses up to 40 GHz.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114370610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499937
J.S. Tsai, Y. Su, J.W. Hsu, J.L. Yang, J. Shieh, S. Jang, M. Liang
This work investigates the leakage and breakdown mechanisms in a Cu damascene structure with carbon-doped CVD extra low-k material (ELK, k=2.5) as intermetal dielectric. The effects of ash processing by inductively coupled plasma (ICP) and reactive ion etching (RIE) modes were extensively characterized. Due to the dominance of Frenkel-Poole (FP) emission in the leakage mechanism between Cu lines, we extracted for the first time the effective k through leakage measurements under various ash conditions. We demonstrate that RIE ash is promising to reduce leakage current, to improve dielectric breakdown, and to retain effective k for Cu/ELK applications. Finally, the mechanisms of ELK damages by ICP and RIE ash are explained.
{"title":"Effect of ash process on leakage mechanism of Cu/ELK (k=2.5) interconnect for 65/45 nm generation","authors":"J.S. Tsai, Y. Su, J.W. Hsu, J.L. Yang, J. Shieh, S. Jang, M. Liang","doi":"10.1109/IITC.2005.1499937","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499937","url":null,"abstract":"This work investigates the leakage and breakdown mechanisms in a Cu damascene structure with carbon-doped CVD extra low-k material (ELK, k=2.5) as intermetal dielectric. The effects of ash processing by inductively coupled plasma (ICP) and reactive ion etching (RIE) modes were extensively characterized. Due to the dominance of Frenkel-Poole (FP) emission in the leakage mechanism between Cu lines, we extracted for the first time the effective k through leakage measurements under various ash conditions. We demonstrate that RIE ash is promising to reduce leakage current, to improve dielectric breakdown, and to retain effective k for Cu/ELK applications. Finally, the mechanisms of ELK damages by ICP and RIE ash are explained.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127639697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499928
N. Nagaraj, W. Hunter, P. Chidambaram, T. Garibay, U. Narasimha, A. Hill, H. Shichijo
The impact of interconnect technology scaling on RC delay is a well-researched topic. This paper provides a fresh perspective on the impact of interconnect technology scaling on SOC designs. The impact of intra-cell RC parameters on circuit performance is described. The importance of managing the intra-cell RC scaling for low power designs is emphasized. The impact of fill metal and CMP on analog circuits is illustrated. The significance of accurate RC extraction for validating the performance and signal integrity of SOC designs is discussed. Using a 64M transistor SOC design, the effects of noise and EM reliability are highlighted. The impact of inductance on clock skew, noise and reliability are discussed.
{"title":"Impact of interconnect technology scaling on SOC design methodologies","authors":"N. Nagaraj, W. Hunter, P. Chidambaram, T. Garibay, U. Narasimha, A. Hill, H. Shichijo","doi":"10.1109/IITC.2005.1499928","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499928","url":null,"abstract":"The impact of interconnect technology scaling on RC delay is a well-researched topic. This paper provides a fresh perspective on the impact of interconnect technology scaling on SOC designs. The impact of intra-cell RC parameters on circuit performance is described. The importance of managing the intra-cell RC scaling for low power designs is emphasized. The impact of fill metal and CMP on analog circuits is illustrated. The significance of accurate RC extraction for validating the performance and signal integrity of SOC designs is discussed. Using a 64M transistor SOC design, the effects of noise and EM reliability are highlighted. The impact of inductance on clock skew, noise and reliability are discussed.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127385014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499958
R. Deng, S. Dunham
We use a quantum mechanical calculation of momentum loss rates as function of spatial frequency of surface roughness to identify which frequencies contribute most strongly to conductivity degradation. We combine these calculations with surface roughness spectrum from atomic step model matched to AFM data. We find that roughness with period on the order of 300 nm gives greatest contribution to resistance increase, but that scattering from typical Cu surfaces can be expected to be nearly specular. We attribute apparent surface scattering to adhesion/barrier layer properties rather than interface or surface roughness.
{"title":"Analysis of surface roughness scattering and its contribution to conductivity degradation in nanoscale interconnects","authors":"R. Deng, S. Dunham","doi":"10.1109/IITC.2005.1499958","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499958","url":null,"abstract":"We use a quantum mechanical calculation of momentum loss rates as function of spatial frequency of surface roughness to identify which frequencies contribute most strongly to conductivity degradation. We combine these calculations with surface roughness spectrum from atomic step model matched to AFM data. We find that roughness with period on the order of 300 nm gives greatest contribution to resistance increase, but that scattering from typical Cu surfaces can be expected to be nearly specular. We attribute apparent surface scattering to adhesion/barrier layer properties rather than interface or surface roughness.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117281795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499905
M. Tagami, H. Ohtake, M. Abe, F. Ito, T. Takeuchi, K. Ohto, T. Usami, M. Suzuki, T. Suzuki, N. Sashida, Y. Hayashi
Chip packaging technology with a circuit-under-pad (CUP) structure is developed for porous SiOCH (k=2.55)/Cu dual-damascene interconnects. Wire bonding damage is mainly improved by the pad structure. For the molding process, it is important to decrease the coefficient of thermal expansion (CTE) of the molding compounds. Combining the stress controls in these packaging processes with the contrived low-k deposition, high performance 65 nm-node ULSI chips are furnished in low-cost QFP with conventional wire bonding.
{"title":"Comprehensive process design for low-cost chip packaging with circuit-under-pad (CUP) structure in porous-SiOCH film","authors":"M. Tagami, H. Ohtake, M. Abe, F. Ito, T. Takeuchi, K. Ohto, T. Usami, M. Suzuki, T. Suzuki, N. Sashida, Y. Hayashi","doi":"10.1109/IITC.2005.1499905","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499905","url":null,"abstract":"Chip packaging technology with a circuit-under-pad (CUP) structure is developed for porous SiOCH (k=2.55)/Cu dual-damascene interconnects. Wire bonding damage is mainly improved by the pad structure. For the molding process, it is important to decrease the coefficient of thermal expansion (CTE) of the molding compounds. Combining the stress controls in these packaging processes with the contrived low-k deposition, high performance 65 nm-node ULSI chips are furnished in low-cost QFP with conventional wire bonding.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124617863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：