A new SSS-OSELO technology for 0.15-/spl mu/m low-defect isolation

Y. Sudoh, T. Kaga, J. Yugami, T. Kure
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引用次数: 1

Abstract

A new isolation with single-Si/sub 3/N/sub 4/-spacer (SSS) OSELO technology is proposed. The features of the SSS OSELO process are low bird's beak penetration and low defect isolation, which are achieved by using low defect-density etching for the Si/sub 3/N/sub 4/ spacer formation, and lower growth-rate and/or a high-temperature oxidation ambient. The SSS OSELO technology allows the 0.15-/spl mu/m low-defect isolation and the fabrication of 1-gigabit DRAM cells.
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一种新的ss - oselo技术,用于0.15-/spl mu/m的低缺陷隔离
提出了一种新的单si /sub - 3/N/sub - 4/间隔(SSS) OSELO隔离技术。SSS OSELO工艺的特点是低鸟喙穿透和低缺陷隔离,这是通过对Si/sub - 3/N/sub - 4/间隔层使用低缺陷密度蚀刻来实现的,以及较低的生长速率和/或高温氧化环境。SSS OSELO技术允许0.15-/spl mu/m的低缺陷隔离和1千兆DRAM单元的制造。
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Semiconductor CIM system, innovation toward the year 2000 CVD SiN/sub X/ anti-reflective coating for sub-0.5 /spl mu/m lithography Advantage of small geometry silicon MOSFETs for high-frequency analog applications under low power supply voltage of 0.5 V The influence of oxygen at epitaxial Si/Si substrate interface for 0.1 /spl mu/m epitaxial Si channel N-MOSFETs grown by UHV-CVD High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: /spl Psi/) SOI wafer
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