Submicron Lithography Enabling Panel Based Heterogeneous Integration

Doug Shelton, Ken-ichiro Mori, Y. Goto, Hiroyuki Wada, Hideo Tanaka, Hiromi Suda, Seiya Miura
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Abstract

High-Performance Computing (HPC) systems increasingly adopt Heterogeneous Integration (HI) technologies that utilize large substrates and high-resolution processes to facilitate die and chiplet. Fan-Out Wafer Level Packaging (FOWLP) and silicon interposers using high-density Redistribution Layers (RDL) can help maximize bandwidth and performance but HI roadmaps require improvements in resolution and lower costs to enable wide adoption of these More-than-Moore technologies. Panel based processes can provide cost advantages compared to wafer processes for fabrication of large interposers and Fan-Out packages. Panel based SiP processes however demand submicron resolution over a large field size and uniform exposure across large panels. To meet these challenges, Canon developed the first lithography exposure system capable of achieving submicron resolution on large panels. The new panel exposure tool targets 0.8 μm design rules and utilizes a new panel handling system and stage that allows processing of panels as large as 515 × 515 mm. The new panel exposure tool is equipped with a UL82 wide-field projection lens with a maximum Numerical Aperture (NA) of 0.24 and offers a 52 × 68 mm exposure field for large device fabrication without stitching adjacent shots. Fine-RDL lithography systems must provide a large Depth-of-Focus (DoF) to maintain pattern fidelity to maximize DoF, the new panel exposure tool applies die-by-die focus and tilt compensation and functions to compensate for panel warpage. Process factors related to DoF include panel flatness and photoresist materials and film uniformity. This paper details test results from a panel exposure system that confirms the feasibility and advantages of submicron panel processes. We also introduce additional challenges related to panel processes including slit-coater uniformity, photo resist materials and panel flatness. We will present data illustrating that new panel exposure tool can provide excellent resolution across large exposure fields on panels to enable HI innovation.
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亚微米光刻实现基于面板的异构集成
高性能计算(HPC)系统越来越多地采用异构集成(HI)技术,这些技术利用大型基板和高分辨率工艺来促进芯片和芯片的发展。扇出晶圆级封装(FOWLP)和使用高密度再分布层(RDL)的硅中间层可以帮助最大限度地提高带宽和性能,但HI路线图需要提高分辨率和降低成本,才能广泛采用这些“超越摩尔”技术。与制造大型中间层和扇出封装的晶圆工艺相比,基于面板的工艺可以提供成本优势。然而,基于面板的SiP工艺要求在大视场尺寸上实现亚微米级的分辨率,并在大面板上均匀曝光。为了应对这些挑战,佳能开发了第一个能够在大型面板上实现亚微米分辨率的光刻曝光系统。新的面板曝光工具针对0.8 μm的设计规则,采用新的面板处理系统和工作台,可以处理515 × 515 mm的面板。新的面板曝光工具配备了UL82宽视场投影镜头,最大数值孔径(NA)为0.24,并提供52 × 68 mm的曝光场,用于大型器件制造,而无需拼接相邻镜头。Fine-RDL光刻系统必须提供大的焦深(DoF)以保持图案保真度以最大化DoF,新的面板曝光工具采用逐模对焦和倾斜补偿以及补偿面板翘曲的功能。与DoF相关的工艺因素包括面板平整度、光刻胶材料和薄膜均匀性。本文详细介绍了面板曝光系统的测试结果,证实了亚微米面板工艺的可行性和优越性。我们还介绍了与面板工艺相关的其他挑战,包括狭缝涂布机均匀性,光刻胶材料和面板平整度。我们将展示数据,说明新的面板曝光工具可以在面板上的大曝光场上提供出色的分辨率,从而实现HI创新。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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