Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375894
N. Lakhera, B. Carpenter, Trung Duong, Mollie Benson, A. Mawer
Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry's first auto grade 1 capable large WLCSP package. (∼ 72 mm2 body size, 18×15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a −40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.
{"title":"Board Level Reliability of Automotive Grade WLCSP for Radar Applications","authors":"N. Lakhera, B. Carpenter, Trung Duong, Mollie Benson, A. Mawer","doi":"10.23919/IWLPC52010.2020.9375894","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375894","url":null,"abstract":"Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry's first auto grade 1 capable large WLCSP package. (∼ 72 mm2 body size, 18×15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a −40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122741633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375884
Guilian Gao, J. Theil, G. Fountain, Thomas Workman, Gabe Guevara, C. Uzoh, D. Suwito, Bongsub Lee, K.M. Bang, R. Katkar, L. Mirkarimi
The Direct Bond Interconnect (DBI® Ultra) technology is a low temperature die to wafer (D2W) and die to die (D2D) hybrid bonding technology that solves many challenges with pitch scaling in advanced packaging. The ability to scale to < 1μm pitch while maintaining throughput comparable to the mass reflow flip chip process and providing improved reliability performance makes this platform technology attractive for the next generation packaging in the semiconductor industry. Two application areas which will benefit significantly in the migration from Cu μbump or Cu pillar to an all-Cu interconnect are high bandwidth memory (HBM) and compute intensive applications in 2.5D and 3D integrated solutions. A critical enabler of the D2W hybrid bonding technology in high volume manufacturing (HVM) is the availability of suitable pick and place bonders. The D2W hybrid bonding task is very similar to flip chip but require enhanced cleanliness environments with the bonder to perform ultra clean bonding. Currently, high alignment accuracy HVM bonders such as the Besi Chameo 8800 achieve approximately 3 μmalignment accuracy without sacrificing throughput and offer cleanroom environmental kits. These bonders accommodate device interconnect pitches of approximately 30 μmor larger. We target the first D2W bonding adoption in the sub-40 μmpitch range using existing flip chip bonders. Ziptronix first demonstrated the D2W hybrid bonding in 2003. Over the last five years Xperi has been systemically addressing critical challenges to bring the hybrid bonding technology for D2W applications to a manufacturing readiness. We present a review of the progress in this paper. Recently we have fabricated a test vehicle with TSVs similar to a HBM DRAM footprint to build 4-die stacks to demonstrate stacking and TSV intergration with the technology. The die is 8mm x12mm and 50 μmthick. TSV arrays include areas with up to 9480 TSV s in each die with a diameter of 5 μmon a pitch of35 μmThe fabrication of the hybrid bonding interface represents a significant simplification compared to the solder micro-bump technology. The Cu-Cu interconnectwas formed at 200°C. We share the assembly results of the 4 die stacks with TSV s in this paper.
{"title":"Die to Wafer Hybrid Bonding: Multi-Die Stacking with Tsv Integration","authors":"Guilian Gao, J. Theil, G. Fountain, Thomas Workman, Gabe Guevara, C. Uzoh, D. Suwito, Bongsub Lee, K.M. Bang, R. Katkar, L. Mirkarimi","doi":"10.23919/IWLPC52010.2020.9375884","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375884","url":null,"abstract":"The Direct Bond Interconnect (DBI® Ultra) technology is a low temperature die to wafer (D2W) and die to die (D2D) hybrid bonding technology that solves many challenges with pitch scaling in advanced packaging. The ability to scale to < 1μm pitch while maintaining throughput comparable to the mass reflow flip chip process and providing improved reliability performance makes this platform technology attractive for the next generation packaging in the semiconductor industry. Two application areas which will benefit significantly in the migration from Cu μbump or Cu pillar to an all-Cu interconnect are high bandwidth memory (HBM) and compute intensive applications in 2.5D and 3D integrated solutions. A critical enabler of the D2W hybrid bonding technology in high volume manufacturing (HVM) is the availability of suitable pick and place bonders. The D2W hybrid bonding task is very similar to flip chip but require enhanced cleanliness environments with the bonder to perform ultra clean bonding. Currently, high alignment accuracy HVM bonders such as the Besi Chameo 8800 achieve approximately 3 μmalignment accuracy without sacrificing throughput and offer cleanroom environmental kits. These bonders accommodate device interconnect pitches of approximately 30 μmor larger. We target the first D2W bonding adoption in the sub-40 μmpitch range using existing flip chip bonders. Ziptronix first demonstrated the D2W hybrid bonding in 2003. Over the last five years Xperi has been systemically addressing critical challenges to bring the hybrid bonding technology for D2W applications to a manufacturing readiness. We present a review of the progress in this paper. Recently we have fabricated a test vehicle with TSVs similar to a HBM DRAM footprint to build 4-die stacks to demonstrate stacking and TSV intergration with the technology. The die is 8mm x12mm and 50 μmthick. TSV arrays include areas with up to 9480 TSV s in each die with a diameter of 5 μmon a pitch of35 μmThe fabrication of the hybrid bonding interface represents a significant simplification compared to the solder micro-bump technology. The Cu-Cu interconnectwas formed at 200°C. We share the assembly results of the 4 die stacks with TSV s in this paper.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131644944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375866
Keith Bryant, B. Eng
Today's consumers are looking for powerful, multifunctional electronic devices with unprecedented performance and speed, yet small, thin and low cost. This creates complex technology and manufacturing challenges for semiconductor companies as they look for new ways to achieve greater performance and functionality in a small, thin, low cost device. JCET is an industry leader in Wafer Level Packaging (WLP) technology, providing a comprehensive portfolio of WLP solutions including Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP) and Integrated Passive Devices (IPD This paper shares data and results from our labs and those of our technology partners which come from two recent tube technology advances, both show great potential for providing solutions to the issues of imaging small features quickly, faced in the higher end semiconductor manufacturing industry. Metal Jet Technology, in metal jet anode microfocus xray tubes the traditional solid metal anode is replaced with a jet of liquid metal, which acts as the electron-beam target, The metal jet supports higher electron-beam power and can therefore generate higher X-ray flux. The major benefit of the increased power density level for the metal-jet X-ray tube is the possibility to operate with a smaller focal spot, say 5 ?m, to increase image resolution and at the same time acquire the image faster, since the power is 10x higher for same spot size. Which means that a 5μm spot on a Metal Jet can tolerate approximately 5x higher power compared to a 10μm spot on a tube with a traditional solid filament This technology delivers one of the smallest and most intensive X-ray beams of any Xray source to meet the ever-increasing technology demands, including wafer level package inspection. Nano Tube Technology This enables industry-leading resolution in geometric magnification, the Nano tube is based on advanced electron optics and the latest tungsten-diamond transmission target technology. Automatic e-beam focusing, and astigmatism correction ensures that the smallest possible, truly round spot is achieved. The Nano tube also has the unique feature of internally measuring and reporting the current spot size. In addition, advanced cooling and thermal design results in extreme stability over time. This enables an unprecedented true resolution of 150 nm lines and spaces. The true round spot of the tube is demonstrated by the highly symmetric images of a ‘Siemens star’ resolution target, the innermost features are 150 nm
{"title":"New X-Ray Tubes for Wafer Level Inspection","authors":"Keith Bryant, B. Eng","doi":"10.23919/IWLPC52010.2020.9375866","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375866","url":null,"abstract":"Today's consumers are looking for powerful, multifunctional electronic devices with unprecedented performance and speed, yet small, thin and low cost. This creates complex technology and manufacturing challenges for semiconductor companies as they look for new ways to achieve greater performance and functionality in a small, thin, low cost device. JCET is an industry leader in Wafer Level Packaging (WLP) technology, providing a comprehensive portfolio of WLP solutions including Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP) and Integrated Passive Devices (IPD This paper shares data and results from our labs and those of our technology partners which come from two recent tube technology advances, both show great potential for providing solutions to the issues of imaging small features quickly, faced in the higher end semiconductor manufacturing industry. Metal Jet Technology, in metal jet anode microfocus xray tubes the traditional solid metal anode is replaced with a jet of liquid metal, which acts as the electron-beam target, The metal jet supports higher electron-beam power and can therefore generate higher X-ray flux. The major benefit of the increased power density level for the metal-jet X-ray tube is the possibility to operate with a smaller focal spot, say 5 ?m, to increase image resolution and at the same time acquire the image faster, since the power is 10x higher for same spot size. Which means that a 5μm spot on a Metal Jet can tolerate approximately 5x higher power compared to a 10μm spot on a tube with a traditional solid filament This technology delivers one of the smallest and most intensive X-ray beams of any Xray source to meet the ever-increasing technology demands, including wafer level package inspection. Nano Tube Technology This enables industry-leading resolution in geometric magnification, the Nano tube is based on advanced electron optics and the latest tungsten-diamond transmission target technology. Automatic e-beam focusing, and astigmatism correction ensures that the smallest possible, truly round spot is achieved. The Nano tube also has the unique feature of internally measuring and reporting the current spot size. In addition, advanced cooling and thermal design results in extreme stability over time. This enables an unprecedented true resolution of 150 nm lines and spaces. The true round spot of the tube is demonstrated by the highly symmetric images of a ‘Siemens star’ resolution target, the innermost features are 150 nm","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114217507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375903
R. Pahwa, S. W. Ho, Ren Qin, Richard Chang, Oo Zaw Min, Jie Wang, V. S. Rao, T. Nwe, Yanjing Yang, J. Neumann, R. Pichumani, T. Gregorich
For over 40 years lithographic silicon scaling has driven circuit integration and performance improvement in the semiconductor industry. As silicon scaling slows down, the industry is increasingly dependent on IC package technologies to contribute to further circuit integration and performance improvements. This is a paradigm-shift and requires the IC package industry to reduce the size and increase the density of internal interconnects on a scale which has never been done before. Traditional package characterization and process optimization relies on destructive techniques such as physical cross-sections and delayering to extract data from internal package features. These destructive techniques are not practical with today's advanced packages. In this paper we will demonstrate how data acquired nondestructively with a 3D X-ray microscope can be enhanced and optimized using machine learning, and can then be used to measure, characterize and optimize the design and production of buried interconnects in advanced IC packages. Test vehicles replicating 2.5D and HBM construction were designed and fabricated, and digital data was extracted from these test vehicles using 3D X-ray and machine learning techniques. The extracted digital data was used to characterize and optimize the design and production of the interconnects and demonstrates a superior alternative to destructive physical analysis. We report a mAP of 0.96 for 3D object detection, a dice score of 0.92 for 3D segmentation and an average of 2.1 um error for 3D metrology on the test dataset. This paper is the first part of a multi-part report.
{"title":"Machine-Learning Based Methodologies for 3D X-Ray Measurement, Characterization and Optimization for Buried Structures in Advanced IC Packages","authors":"R. Pahwa, S. W. Ho, Ren Qin, Richard Chang, Oo Zaw Min, Jie Wang, V. S. Rao, T. Nwe, Yanjing Yang, J. Neumann, R. Pichumani, T. Gregorich","doi":"10.23919/IWLPC52010.2020.9375903","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375903","url":null,"abstract":"For over 40 years lithographic silicon scaling has driven circuit integration and performance improvement in the semiconductor industry. As silicon scaling slows down, the industry is increasingly dependent on IC package technologies to contribute to further circuit integration and performance improvements. This is a paradigm-shift and requires the IC package industry to reduce the size and increase the density of internal interconnects on a scale which has never been done before. Traditional package characterization and process optimization relies on destructive techniques such as physical cross-sections and delayering to extract data from internal package features. These destructive techniques are not practical with today's advanced packages. In this paper we will demonstrate how data acquired nondestructively with a 3D X-ray microscope can be enhanced and optimized using machine learning, and can then be used to measure, characterize and optimize the design and production of buried interconnects in advanced IC packages. Test vehicles replicating 2.5D and HBM construction were designed and fabricated, and digital data was extracted from these test vehicles using 3D X-ray and machine learning techniques. The extracted digital data was used to characterize and optimize the design and production of the interconnects and demonstrates a superior alternative to destructive physical analysis. We report a mAP of 0.96 for 3D object detection, a dice score of 0.92 for 3D segmentation and an average of 2.1 um error for 3D metrology on the test dataset. This paper is the first part of a multi-part report.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123288423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375876
P. Ye, Jianwen Han, Stephan Braye, Kyle Whitten, Rich Hurtubise, T. Richardson, E. Najjar
We developed a direct current, electrochemical plating process to control the formation of nano-twinned copper (nt-Cu) to fulfill the keen market interest for copper-to-copper direct bonding, or hybrid-bonding, for wafer-level packaging applications. Unlike other studies that require either pulse plating or high agitation for nt-Cu formation, this newly designed process can produce nt-Cu without pulse plating, and under low agitation conditions. The microstructure transition between the seed layer and nt-Cu formation happens in less than 0.50 μm. In this paper, we will discuss three different formulations that enable nt-Cu creation. We will also address the effects of current density (CD), additive concentration, nucleation density, agitation, and their relevance to the nt-Cu formation. We achieve close to 100% columnar grains of nt-Cu with Twin Boundary (TB) parallel to the substrate surface when deposited on (111) texture dominated Cu substrate. The strong interaction of additive with the copper seed layer plays a crucial role in the fast nt-Cu initiation and growth. Current density and nucleation density also play an essential role in the nt-Cu formation. Some level of additive adsorption is necessary to enable the critical nucleation density for a fast nt-Cu initiation, which increases with increasing current density. Nano-twinned Cu grain size decreases with rising deposition rate. However, further increases in deposition rate result in a slightly larger nt-Cu grain size. We can produce a uniform nt-Cu with a grain size of a few hundreds of nanometers when the current density is in the range of 30 to 60 mA/cm2, and additive concentration is 2.0 ml/L to 6.0 ml/L. Either strong or weak convection has minor effects on nt-Cu formation. With this process, an nt-Cu configuration is possible when plating regular pillar structures but also enables nano-twinned copper deposition for RDL lines and vias with recess.
{"title":"Electrochemical Plating of Nano-Twinned Cu for WLP Applications","authors":"P. Ye, Jianwen Han, Stephan Braye, Kyle Whitten, Rich Hurtubise, T. Richardson, E. Najjar","doi":"10.23919/IWLPC52010.2020.9375876","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375876","url":null,"abstract":"We developed a direct current, electrochemical plating process to control the formation of nano-twinned copper (nt-Cu) to fulfill the keen market interest for copper-to-copper direct bonding, or hybrid-bonding, for wafer-level packaging applications. Unlike other studies that require either pulse plating or high agitation for nt-Cu formation, this newly designed process can produce nt-Cu without pulse plating, and under low agitation conditions. The microstructure transition between the seed layer and nt-Cu formation happens in less than 0.50 μm. In this paper, we will discuss three different formulations that enable nt-Cu creation. We will also address the effects of current density (CD), additive concentration, nucleation density, agitation, and their relevance to the nt-Cu formation. We achieve close to 100% columnar grains of nt-Cu with Twin Boundary (TB) parallel to the substrate surface when deposited on (111) texture dominated Cu substrate. The strong interaction of additive with the copper seed layer plays a crucial role in the fast nt-Cu initiation and growth. Current density and nucleation density also play an essential role in the nt-Cu formation. Some level of additive adsorption is necessary to enable the critical nucleation density for a fast nt-Cu initiation, which increases with increasing current density. Nano-twinned Cu grain size decreases with rising deposition rate. However, further increases in deposition rate result in a slightly larger nt-Cu grain size. We can produce a uniform nt-Cu with a grain size of a few hundreds of nanometers when the current density is in the range of 30 to 60 mA/cm2, and additive concentration is 2.0 ml/L to 6.0 ml/L. Either strong or weak convection has minor effects on nt-Cu formation. With this process, an nt-Cu configuration is possible when plating regular pillar structures but also enables nano-twinned copper deposition for RDL lines and vias with recess.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"1997 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128212310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375886
Debbie Claire Sanchez, Klemens Reitinger, Sophia Oldeide, Wenxuan Song
This paper intends to provide insight into the complexities of processing large panel format for Fan-out. It explicitly tackles handling and thermal treatment during the thermal debonding process, which is the method of separating the molded Fan-out panel from the metal plate carrier bonded by a thermal sensitive double-sided tape. Fan-out encounters two prevalent issues inherent to the structure of the package; die-shift and warpage. Both will be covered and have been taken into account in defining the correct process flow and control of panel-level thermal debonding. The handling mechanism of the panel will play a significant role in eliminating potential handling-induced factors. Thermal control, on the other hand, is essential to control die shift caused by any thermal introduction. This paper details how mechanical design, handling, and thermal control come into play to ensure that common issues for a Fan-out structure are also addressed in panel-level form. Different panel matrix layout is examined to identify how it reacts with the optimized process flow.
{"title":"Handling of Different FOPLP Layouts on Large Area Thermal Chucks","authors":"Debbie Claire Sanchez, Klemens Reitinger, Sophia Oldeide, Wenxuan Song","doi":"10.23919/IWLPC52010.2020.9375886","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375886","url":null,"abstract":"This paper intends to provide insight into the complexities of processing large panel format for Fan-out. It explicitly tackles handling and thermal treatment during the thermal debonding process, which is the method of separating the molded Fan-out panel from the metal plate carrier bonded by a thermal sensitive double-sided tape. Fan-out encounters two prevalent issues inherent to the structure of the package; die-shift and warpage. Both will be covered and have been taken into account in defining the correct process flow and control of panel-level thermal debonding. The handling mechanism of the panel will play a significant role in eliminating potential handling-induced factors. Thermal control, on the other hand, is essential to control die shift caused by any thermal introduction. This paper details how mechanical design, handling, and thermal control come into play to ensure that common issues for a Fan-out structure are also addressed in panel-level form. Different panel matrix layout is examined to identify how it reacts with the optimized process flow.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115804908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375865
Chihiro Funakoshi, D. Shibata, Daichi Okamoto, Y. Shibasaki, Yuya Suzuki
This paper reports a new dry-film type photo imageable dielectric (PID) material with fine patterning capability, which is suitable for FOWLP, FOPLP, and high density package substrates. Features of this material are; 1) Dry-film type for high surface planarity, 2) Low curing temperature (180 deg. C), 3) Low coefficient of thermal expansion (CTE), 4) High resolution for 6–10 μm via formation, 5) Resistance to organic solvents, and 6) High dielectric reliability. Flatness of the surface is advantageous for multi -layering, as well as fine pitch circuit patterning by semi-additive process (SAP). Low curing temperature is beneficial for reduction in internal stress. This PID has both low CTE of 35–45 ppm/deg. C and high resolution below $10 mu mathrm{m}$ which is excellent for multilayer RDL structures. This study focuses on how to improve solvent resistance and dielectric resistance of PID materials by material design. This study also performed reliability demonstration of the biased highly accelerated stress test (BHAST) with the PID material. Cu comb structures with line & space (L/S) = 2/2 μm were formed on the PID material by SAP and electrical voltage was applied under high temperature & moisture condition. It was confirmed that the PID material has high insulation reliability and kept more than 300 hours without electrical failure.
{"title":"High Resolution Dry-film Photo Imageable Dielectric (PID) Material for Fowlp, Foplp, and High Density Package Substrates","authors":"Chihiro Funakoshi, D. Shibata, Daichi Okamoto, Y. Shibasaki, Yuya Suzuki","doi":"10.23919/IWLPC52010.2020.9375865","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375865","url":null,"abstract":"This paper reports a new dry-film type photo imageable dielectric (PID) material with fine patterning capability, which is suitable for FOWLP, FOPLP, and high density package substrates. Features of this material are; 1) Dry-film type for high surface planarity, 2) Low curing temperature (180 deg. C), 3) Low coefficient of thermal expansion (CTE), 4) High resolution for 6–10 μm via formation, 5) Resistance to organic solvents, and 6) High dielectric reliability. Flatness of the surface is advantageous for multi -layering, as well as fine pitch circuit patterning by semi-additive process (SAP). Low curing temperature is beneficial for reduction in internal stress. This PID has both low CTE of 35–45 ppm/deg. C and high resolution below $10 mu mathrm{m}$ which is excellent for multilayer RDL structures. This study focuses on how to improve solvent resistance and dielectric resistance of PID materials by material design. This study also performed reliability demonstration of the biased highly accelerated stress test (BHAST) with the PID material. Cu comb structures with line & space (L/S) = 2/2 μm were formed on the PID material by SAP and electrical voltage was applied under high temperature & moisture condition. It was confirmed that the PID material has high insulation reliability and kept more than 300 hours without electrical failure.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126734699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-Performance Computing (HPC) systems increasingly adopt Heterogeneous Integration (HI) technologies that utilize large substrates and high-resolution processes to facilitate die and chiplet. Fan-Out Wafer Level Packaging (FOWLP) and silicon interposers using high-density Redistribution Layers (RDL) can help maximize bandwidth and performance but HI roadmaps require improvements in resolution and lower costs to enable wide adoption of these More-than-Moore technologies. Panel based processes can provide cost advantages compared to wafer processes for fabrication of large interposers and Fan-Out packages. Panel based SiP processes however demand submicron resolution over a large field size and uniform exposure across large panels. To meet these challenges, Canon developed the first lithography exposure system capable of achieving submicron resolution on large panels. The new panel exposure tool targets 0.8 μm design rules and utilizes a new panel handling system and stage that allows processing of panels as large as 515 × 515 mm. The new panel exposure tool is equipped with a UL82 wide-field projection lens with a maximum Numerical Aperture (NA) of 0.24 and offers a 52 × 68 mm exposure field for large device fabrication without stitching adjacent shots. Fine-RDL lithography systems must provide a large Depth-of-Focus (DoF) to maintain pattern fidelity to maximize DoF, the new panel exposure tool applies die-by-die focus and tilt compensation and functions to compensate for panel warpage. Process factors related to DoF include panel flatness and photoresist materials and film uniformity. This paper details test results from a panel exposure system that confirms the feasibility and advantages of submicron panel processes. We also introduce additional challenges related to panel processes including slit-coater uniformity, photo resist materials and panel flatness. We will present data illustrating that new panel exposure tool can provide excellent resolution across large exposure fields on panels to enable HI innovation.
{"title":"Submicron Lithography Enabling Panel Based Heterogeneous Integration","authors":"Doug Shelton, Ken-ichiro Mori, Y. Goto, Hiroyuki Wada, Hideo Tanaka, Hiromi Suda, Seiya Miura","doi":"10.23919/IWLPC52010.2020.9375902","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375902","url":null,"abstract":"High-Performance Computing (HPC) systems increasingly adopt Heterogeneous Integration (HI) technologies that utilize large substrates and high-resolution processes to facilitate die and chiplet. Fan-Out Wafer Level Packaging (FOWLP) and silicon interposers using high-density Redistribution Layers (RDL) can help maximize bandwidth and performance but HI roadmaps require improvements in resolution and lower costs to enable wide adoption of these More-than-Moore technologies. Panel based processes can provide cost advantages compared to wafer processes for fabrication of large interposers and Fan-Out packages. Panel based SiP processes however demand submicron resolution over a large field size and uniform exposure across large panels. To meet these challenges, Canon developed the first lithography exposure system capable of achieving submicron resolution on large panels. The new panel exposure tool targets 0.8 μm design rules and utilizes a new panel handling system and stage that allows processing of panels as large as 515 × 515 mm. The new panel exposure tool is equipped with a UL82 wide-field projection lens with a maximum Numerical Aperture (NA) of 0.24 and offers a 52 × 68 mm exposure field for large device fabrication without stitching adjacent shots. Fine-RDL lithography systems must provide a large Depth-of-Focus (DoF) to maintain pattern fidelity to maximize DoF, the new panel exposure tool applies die-by-die focus and tilt compensation and functions to compensate for panel warpage. Process factors related to DoF include panel flatness and photoresist materials and film uniformity. This paper details test results from a panel exposure system that confirms the feasibility and advantages of submicron panel processes. We also introduce additional challenges related to panel processes including slit-coater uniformity, photo resist materials and panel flatness. We will present data illustrating that new panel exposure tool can provide excellent resolution across large exposure fields on panels to enable HI innovation.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116335071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375872
Kath Crook, Mark Carruthers, D. Archard, S. Burgess, K. Buchanan
Advanced packaging technologies, incorporating through-silicon vias (TSVs) have the potential to improve functionality and electrical performance of semiconductor devices in a reduced package size. Such technologies are coming to prominence for devices requiring high bandwidth memory in emerging applications such as self-driving cars, machine learning and real-time speech processing [1]–[3]. In ‘via-middle’ process flows, the TSVs are exposed from the back side of the wafer by grind and plasma etch steps. Dielectric layers deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) serve to passivate and mechanically support the exposed TSV prior to bump/RDL formation and then chip-to-wafer or wafer-to-wafer bonding. Prior to via reveal processing, device wafers are bonded to silicon or glass carriers and thinned to around 50μm. The temporary bonding material imposes a temperature constraint of ~190°C during all subsequent via reveal process steps. This temperature constraint is especially challenging for the PECVD passivation processes where films with stable electrical and mechanical properties are required. Controlling PECVD film stress is also critical as stresses can cause excessive wafer bow in thinned wafers unless countermeasures are taken. While average stress must be controlled, it is also critical to minimize within-wafer stress as this will impact die-level bow and affect subsequent die-attach processes. In this paper, we report on silicon nitride (SiN) - silicon oxide (SiO) stacks deposited at <190°C which give excellent electrical properties with leakage current densities < 1E-9 A.cm-2 and breakdown voltages >10 MV.cm-1. These films are also optimized in terms of step coverage and stress characteristics. Crucially, electrical properties and stack stress are shown to be stable with no moisture absorption or drift in film properties over time when exposed to atmosphere.
{"title":"Optimization of Low Temperature PECVD Dielectric Stacks foR Via Reveal Passivation","authors":"Kath Crook, Mark Carruthers, D. Archard, S. Burgess, K. Buchanan","doi":"10.23919/IWLPC52010.2020.9375872","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375872","url":null,"abstract":"Advanced packaging technologies, incorporating through-silicon vias (TSVs) have the potential to improve functionality and electrical performance of semiconductor devices in a reduced package size. Such technologies are coming to prominence for devices requiring high bandwidth memory in emerging applications such as self-driving cars, machine learning and real-time speech processing [1]–[3]. In ‘via-middle’ process flows, the TSVs are exposed from the back side of the wafer by grind and plasma etch steps. Dielectric layers deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) serve to passivate and mechanically support the exposed TSV prior to bump/RDL formation and then chip-to-wafer or wafer-to-wafer bonding. Prior to via reveal processing, device wafers are bonded to silicon or glass carriers and thinned to around 50μm. The temporary bonding material imposes a temperature constraint of ~190°C during all subsequent via reveal process steps. This temperature constraint is especially challenging for the PECVD passivation processes where films with stable electrical and mechanical properties are required. Controlling PECVD film stress is also critical as stresses can cause excessive wafer bow in thinned wafers unless countermeasures are taken. While average stress must be controlled, it is also critical to minimize within-wafer stress as this will impact die-level bow and affect subsequent die-attach processes. In this paper, we report on silicon nitride (SiN) - silicon oxide (SiO) stacks deposited at <190°C which give excellent electrical properties with leakage current densities < 1E-9 A.cm-2 and breakdown voltages >10 MV.cm-1. These films are also optimized in terms of step coverage and stress characteristics. Crucially, electrical properties and stack stress are shown to be stable with no moisture absorption or drift in film properties over time when exposed to atmosphere.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131607907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375895
Jae-gwon Jang, Kyoung-Lim Suk, S. Lee, Jinha Park, Gwang-jae Jeon, Jung-ho Park, Jeong-gi Jin, Su-chang Lee, Gyoung-bum Kim, Joonhyuk Choi, Dae-woo Kim, D. Oh, Won-Kyoung Choi
As faster data processing and communication gets more demanded for Data Center/Cloud, HPC (High Performance Computing), AI (Artificial Intelligence) accelerator and Network markets, HBM (High Bandwidth Memory) becomes main memory type to meet the required bandwidth performance. HBM integration with logic dies in a system level has been developed on 2.5D SiP (System in Package) Platform with Si Interposer having TSV (Through Silicon Vias) of which fabrication cost is rather high. Therefore, as the low cost solution, alternative 2.5D SiP Platform approaches such as Organic Interposer using Redistribution Layer (RDL) and Glass Interposer have recently been reported. In this paper, RDL Interposer package with 4 HBM and 1 logic is demonstrated as 2.5D package platform based on RDL-First Fan-out Wafer Level Package (FOWLP). The effect of RDL design factors on electrical performances is investigated using the eye diagram method and fine pitch multi-layer RDL structure (2um L/S RDL, 4 Layers) is designed accordingly. Fine pitch RDL process is established followed by the wafer level and unit level assembly processes and RDL Interposer package is confirmed to meet all the reliability requirements.
{"title":"Advanced RDL Interposer PKG Technology for Heterogeneous Integration","authors":"Jae-gwon Jang, Kyoung-Lim Suk, S. Lee, Jinha Park, Gwang-jae Jeon, Jung-ho Park, Jeong-gi Jin, Su-chang Lee, Gyoung-bum Kim, Joonhyuk Choi, Dae-woo Kim, D. Oh, Won-Kyoung Choi","doi":"10.23919/IWLPC52010.2020.9375895","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375895","url":null,"abstract":"As faster data processing and communication gets more demanded for Data Center/Cloud, HPC (High Performance Computing), AI (Artificial Intelligence) accelerator and Network markets, HBM (High Bandwidth Memory) becomes main memory type to meet the required bandwidth performance. HBM integration with logic dies in a system level has been developed on 2.5D SiP (System in Package) Platform with Si Interposer having TSV (Through Silicon Vias) of which fabrication cost is rather high. Therefore, as the low cost solution, alternative 2.5D SiP Platform approaches such as Organic Interposer using Redistribution Layer (RDL) and Glass Interposer have recently been reported. In this paper, RDL Interposer package with 4 HBM and 1 logic is demonstrated as 2.5D package platform based on RDL-First Fan-out Wafer Level Package (FOWLP). The effect of RDL design factors on electrical performances is investigated using the eye diagram method and fine pitch multi-layer RDL structure (2um L/S RDL, 4 Layers) is designed accordingly. Fine pitch RDL process is established followed by the wafer level and unit level assembly processes and RDL Interposer package is confirmed to meet all the reliability requirements.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126934891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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