{"title":"Low capacitance multilevel interconnection using low-/spl epsi/ organic spin-on glass for quarter-micron high-speed ULSIs","authors":"T. Furusawa, Y. Homma","doi":"10.1109/VLSIT.1995.520857","DOIUrl":null,"url":null,"abstract":"A low capacitance multilevel interconnection for high-speed ULSIs is developed. It employs metal-line spaces filled with only a low-dielectric-constant, reflowable organic spin-on glass (SOG). The SOG-filled dielectrics reduce interconnection-capacitance to about 70% that of conventional structures, and provide a breakdown voltage of 1.7 MV/cm. Low via resistance with via holes down to 0.37 /spl mu/m is achieved using O/sub 2/-RIE (reactive ion etching) surface treatment and a W-plug.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 Symposium on VLSI Technology. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1995.520857","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A low capacitance multilevel interconnection for high-speed ULSIs is developed. It employs metal-line spaces filled with only a low-dielectric-constant, reflowable organic spin-on glass (SOG). The SOG-filled dielectrics reduce interconnection-capacitance to about 70% that of conventional structures, and provide a breakdown voltage of 1.7 MV/cm. Low via resistance with via holes down to 0.37 /spl mu/m is achieved using O/sub 2/-RIE (reactive ion etching) surface treatment and a W-plug.
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