{"title":"Fast ECL-to-CMOS and CMOS-to-ECL translators for an 0.8 mu m BiCMOS gate array","authors":"A. Bass, T.T. Eyck","doi":"10.1109/ASIC.1990.186196","DOIUrl":null,"url":null,"abstract":"Input/output circuits designed to translate from true ECL levels to CMOS levels without bringing a negative supply voltage on the chip are discussed. Using only +5 V and ground eliminates breakdown and parasitic MOSFET problems caused by having both +5 V and -5 V on the chip. These circuits provide an ECL interface to 0.8 mu m BiCMOS gate arrays and are considerably faster than other translators currently available.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"581 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186196","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Input/output circuits designed to translate from true ECL levels to CMOS levels without bringing a negative supply voltage on the chip are discussed. Using only +5 V and ground eliminates breakdown and parasitic MOSFET problems caused by having both +5 V and -5 V on the chip. These circuits provide an ECL interface to 0.8 mu m BiCMOS gate arrays and are considerably faster than other translators currently available.<>
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