Panel: Functional coverage - is your design exposed?

Andrew Piziali, A. Ziv
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Abstract

We prove the correctness of an original method for generating components that capture the occurrence of events, and monitor logical and temporal properties of hardware/software embedded systems. The properties are written in PSL, under the form of assertions in declarative form. The method is based on a library of primitive digital components for the PSL temporal operators. These building blocks are interconnected to construct complex properties, resulting in a synthesizable digital module that can be properly linked to the digital system under scrutiny. The proof reported in this paper applies to the weak version of all "foundation language" operators.
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专题讨论:功能覆盖-您的设计是否暴露?
我们证明了一种原始方法的正确性,该方法用于生成捕获事件发生的组件,并监视硬件/软件嵌入式系统的逻辑和时间属性。这些属性是用PSL编写的,采用声明式断言的形式。该方法基于PSL时间算子的原始数字元件库。这些构建模块相互连接以构建复杂的属性,从而形成一个可合成的数字模块,可以正确地连接到仔细检查的数字系统。本文的证明适用于所有“基础语言”算子的弱版本。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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