{"title":"On the Mitigation of Single Event Transient in 3D LUT by In-Cell Layout Resizing","authors":"S. Azimi, C. De Sio, B. Du, L. Sterpone","doi":"10.1109/RADECS50773.2020.9857719","DOIUrl":null,"url":null,"abstract":"We propose a workflow for the analysis and mitigation of 3D ICs to Single Event Transient by upsizing the sensitive transistors. The workflow is applied to a 45-nm 3D LUT and the results show a 37% reduction in failure rate.","PeriodicalId":371838,"journal":{"name":"2020 20th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"296 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 20th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADECS50773.2020.9857719","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We propose a workflow for the analysis and mitigation of 3D ICs to Single Event Transient by upsizing the sensitive transistors. The workflow is applied to a 45-nm 3D LUT and the results show a 37% reduction in failure rate.
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