K. Fung, T. Suzuki, J. Terazawa, A. Khayami, S. Martindell, C. Blanton, H. Tran, R. Eklund, S. Madan, T. Holloway, M. Rodder, J. Graham, R. Chapman, R. Haken, D. Scott
{"title":"An experimental 5 ns BiCMOS SRAM with a high-speed architecture","authors":"K. Fung, T. Suzuki, J. Terazawa, A. Khayami, S. Martindell, C. Blanton, H. Tran, R. Eklund, S. Madan, T. Holloway, M. Rodder, J. Graham, R. Chapman, R. Haken, D. Scott","doi":"10.1109/VLSIC.1990.111086","DOIUrl":null,"url":null,"abstract":"A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by today's systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-μm BiCMOS technology. The chip is organized as 128 K-words×8-b wide using a 4T2R memory cell of 28 μm2","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1990.111086","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by today's systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-μm BiCMOS technology. The chip is organized as 128 K-words×8-b wide using a 4T2R memory cell of 28 μm2
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