Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111070
T. Iizuka
The strategies for technology integration and design methodologies for embedded memory are discussed as well as testing and yield issues. Some examples of current embedded-memory developments in several representative categories are presented. Owing to rapid progress in Si technology, current high-performance system VLSIs can afford a large embedded memory on chip, which provides wide memory bandwidth, dedicated memory architecture for application, small chip count and compact system, and better system speed scalability along with Si-technology scaling
{"title":"Embedded memory: a key to high performance system VLSIs","authors":"T. Iizuka","doi":"10.1109/VLSIC.1990.111070","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111070","url":null,"abstract":"The strategies for technology integration and design methodologies for embedded memory are discussed as well as testing and yield issues. Some examples of current embedded-memory developments in several representative categories are presented. Owing to rapid progress in Si technology, current high-performance system VLSIs can afford a large embedded memory on chip, which provides wide memory bandwidth, dedicated memory architecture for application, small chip count and compact system, and better system speed scalability along with Si-technology scaling","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129617264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111082
A. Matsuzawa, M. Kagawa, M. Kanoh, S. Tada, S. Nakashima, K. Tatehara, K. Shimizu
The 10-b, 10 MHz BiCMOS A/D (analog-to-digital) converter with a triple-stage conversion scheme, combined with two novel conversion schemes, the dynamic sliding reference method and the triangular interpolation method, has been developed. This novel conversion scheme and BiCMOS circuit technology reduce element counts of bipolar transistors to only 2000. A small active area of 2.5×2.7 mm2 and a low power dissipation of 350 mW with an acceptable SNR (signal-to-noise ratio) of 54 dB including internal sample/hold and reference voltage circuit have been achieved
{"title":"A 10 b 10 MHz triple-stage Bi-CMOS A/D converter","authors":"A. Matsuzawa, M. Kagawa, M. Kanoh, S. Tada, S. Nakashima, K. Tatehara, K. Shimizu","doi":"10.1109/VLSIC.1990.111082","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111082","url":null,"abstract":"The 10-b, 10 MHz BiCMOS A/D (analog-to-digital) converter with a triple-stage conversion scheme, combined with two novel conversion schemes, the dynamic sliding reference method and the triangular interpolation method, has been developed. This novel conversion scheme and BiCMOS circuit technology reduce element counts of bipolar transistors to only 2000. A small active area of 2.5×2.7 mm2 and a low power dissipation of 350 mW with an acceptable SNR (signal-to-noise ratio) of 54 dB including internal sample/hold and reference voltage circuit have been achieved","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126422108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111121
S.C.-M. Chuang, T. Mukherjee, G. Braceras, S. Litten, M. Peters, J. LeBlanc, G. Taroni, C. Akrout
A CMOS VLSI cache memory subsystem, which includes a 72 K cache memory, a 11 K tag memory, a 1.3 K state array, two special buffers, and cache control logic, has been developed and integrated on an experimental microprocessor chip. The unique one-port cache incorporates a reload buffer and a store back buffer to function as a two-port cache, one port for CPU read/write and the other port to the system bus for simultaneous cache reload. The one-port tag also bears pseudo-two-port characteristics by using a cycle-split scheme to access the tag twice in a cache cycle. This allows the tag memory to be used for bus snooping as well as normal cache operation without using the conventional dual-port tag approach to maintain cache data coherency. A unique cache reload mechanism which utilizes the cache read-modify-write cycle is incorporated to maintain data coherency in the reload buffer and store back buffer. This is essential for enhancing snoopy cache performance with pseudo-two-port capability
{"title":"An on-chip 72 K pseudo two-port cache memory subsystem","authors":"S.C.-M. Chuang, T. Mukherjee, G. Braceras, S. Litten, M. Peters, J. LeBlanc, G. Taroni, C. Akrout","doi":"10.1109/VLSIC.1990.111121","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111121","url":null,"abstract":"A CMOS VLSI cache memory subsystem, which includes a 72 K cache memory, a 11 K tag memory, a 1.3 K state array, two special buffers, and cache control logic, has been developed and integrated on an experimental microprocessor chip. The unique one-port cache incorporates a reload buffer and a store back buffer to function as a two-port cache, one port for CPU read/write and the other port to the system bus for simultaneous cache reload. The one-port tag also bears pseudo-two-port characteristics by using a cycle-split scheme to access the tag twice in a cache cycle. This allows the tag memory to be used for bus snooping as well as normal cache operation without using the conventional dual-port tag approach to maintain cache data coherency. A unique cache reload mechanism which utilizes the cache read-modify-write cycle is incorporated to maintain data coherency in the reload buffer and store back buffer. This is essential for enhancing snoopy cache performance with pseudo-two-port capability","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114928830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111100
E. Seevinck
A novel sense-amplifier circuit suitable for fast and large SRAMs in submicron CMOS technology has been proposed. The sense-amplifier is fast, yet very simple, comprising only four transistors. It features a current-sensing character, since it represents a virtual short-circuit to the bitlines, transferring the cell current directly to the output circuits. Sensing delay is rendered insensitive to bitline capacitance, thus easing one of the constraints in memory architecture design: that of restricted bitline length. Current consumption is decreased and yet speed is improved owing to an intrinsic precharge (or dynamic biasing) property. The virtual short-circuit character ensures equal bitline voltages, thus eliminating the need for bitline equalization during a read-access. This could also significantly affect architecture tradeoffs and chip access time
{"title":"A current sense-amplifier for fast CMOS SRAMs","authors":"E. Seevinck","doi":"10.1109/VLSIC.1990.111100","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111100","url":null,"abstract":"A novel sense-amplifier circuit suitable for fast and large SRAMs in submicron CMOS technology has been proposed. The sense-amplifier is fast, yet very simple, comprising only four transistors. It features a current-sensing character, since it represents a virtual short-circuit to the bitlines, transferring the cell current directly to the output circuits. Sensing delay is rendered insensitive to bitline capacitance, thus easing one of the constraints in memory architecture design: that of restricted bitline length. Current consumption is decreased and yet speed is improved owing to an intrinsic precharge (or dynamic biasing) property. The virtual short-circuit character ensures equal bitline voltages, thus eliminating the need for bitline equalization during a read-access. This could also significantly affect architecture tradeoffs and chip access time","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129697866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111076
Y. Nakagome, Y. Kawamoto, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda, K. Itoh
A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future
{"title":"A 1.5 V circuit technology for 64 Mb DRAMs","authors":"Y. Nakagome, Y. Kawamoto, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda, K. Itoh","doi":"10.1109/VLSIC.1990.111076","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111076","url":null,"abstract":"A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128724731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111085
A. Ohba, S. Ohbayashi, T. Shiomi, S. Takano, K. Anami, H. Honda, Y. Ishigaki, M. Hatanaka, S. Nagao, S. Kayano
A 7-ns, 1 M×1/256 K×4 BiCMOS ECL (emitter coupled logic) SRAM with program-free redundancy is described. To obtain the fast address access time and low power consumption, an improved ECL buffer and two-stage sensing scheme were adopted. The SRAM was fabricated with a 0.8-μm double-poly-Si double-metal BiCMOS technology. The RAM has an ECL 10 K interface and operates at a supply voltage of -5.2 V. An access time of 7 ns has been obtained. Active 680 mW for ×4 mode. The cell size is 5.4 μm×7.2 μm (38.88 μm2); the die size is 5.46 mm×16.16 mm (88.24 mm2)
描述了具有无程序冗余的7-ns, 1 M×1/256 K×4 BiCMOS ECL(发射极耦合逻辑)SRAM。为了获得更快的地址访问时间和更低的功耗，采用了改进的ECL缓冲器和两级感知方案。SRAM采用0.8- m双多晶硅双金属BiCMOS技术制备。RAM具有ECL 10 K接口，并在-5.2 V的电源电压下工作。访问时间为7ns。有效值680mw，适用于4次模式。细胞大小为5.4 μ m × 7.2 μ m (38.88 μ m²);模具尺寸为5.46 mm × 16.16 mm (88.24 mm2)
{"title":"A 7 ns 1 Mb BiCMOS ECL SRAM with program-free redundancy","authors":"A. Ohba, S. Ohbayashi, T. Shiomi, S. Takano, K. Anami, H. Honda, Y. Ishigaki, M. Hatanaka, S. Nagao, S. Kayano","doi":"10.1109/VLSIC.1990.111085","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111085","url":null,"abstract":"A 7-ns, 1 M×1/256 K×4 BiCMOS ECL (emitter coupled logic) SRAM with program-free redundancy is described. To obtain the fast address access time and low power consumption, an improved ECL buffer and two-stage sensing scheme were adopted. The SRAM was fabricated with a 0.8-μm double-poly-Si double-metal BiCMOS technology. The RAM has an ECL 10 K interface and operates at a supply voltage of -5.2 V. An access time of 7 ns has been obtained. Active 680 mW for ×4 mode. The cell size is 5.4 μm×7.2 μm (38.88 μm2); the die size is 5.46 mm×16.16 mm (88.24 mm2)","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126521574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111122
K. Uchiyama, H. Aoki, O. Nishii, S. Hatano, O. Nagashima, K. Ooishi, J. Kitano
The authors describe the architecture and design of a second-level cache chip which supports high-speed (160-Mb/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. This chip includes a 32-kB data memory as well as a 42-kb tag memory and 21.7 K-gate logic, and it supports a 50-MHz CPU. Performance and design results are presented
{"title":"Architecture and design of a second-level cache chip with copy-back and 160 MB/s burst-transfer features","authors":"K. Uchiyama, H. Aoki, O. Nishii, S. Hatano, O. Nagashima, K. Ooishi, J. Kitano","doi":"10.1109/VLSIC.1990.111122","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111122","url":null,"abstract":"The authors describe the architecture and design of a second-level cache chip which supports high-speed (160-Mb/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. This chip includes a 32-kB data memory as well as a 42-kb tag memory and 21.7 K-gate logic, and it supports a 50-MHz CPU. Performance and design results are presented","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"357 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115860488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111090
H. Kuriyama, T. Hirose, S. Murakami, T. Wada, K. Fujita, Y. Nishimura, K. Anami
An 8-ns serial access time has been realized in a 4-Mb static RAM with newly proposed circuits (hierarchical shift registers and look-ahead circuits) which can access up to 4 Mb. This memory realizes a 125-MHz fast serial READ/WRITE operation suitable for ultra-high-speed memory systems such as image-processing systems, high-speed testing systems, and supercomputers. This function is also beneficial for reducing the testing time of the RAM
{"title":"A 4-Mbit CMOS SRAM with 8-ns serial-access time","authors":"H. Kuriyama, T. Hirose, S. Murakami, T. Wada, K. Fujita, Y. Nishimura, K. Anami","doi":"10.1109/VLSIC.1990.111090","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111090","url":null,"abstract":"An 8-ns serial access time has been realized in a 4-Mb static RAM with newly proposed circuits (hierarchical shift registers and look-ahead circuits) which can access up to 4 Mb. This memory realizes a 125-MHz fast serial READ/WRITE operation suitable for ultra-high-speed memory systems such as image-processing systems, high-speed testing systems, and supercomputers. This function is also beneficial for reducing the testing time of the RAM","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125179203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111109
H.J. Shin
It has been demonstrated that full-swing complementary MOS/bipolar logic (FS-CMBL) circuits utilizing a push-pull emitter-follower driver and base-emitter shunting to achieve full swing are potentially advantageous for scaled BiCMOS technologies. In these circuits, delay and power consumption depend on characteristics of the base-to-base clamping diode, parasitic capacitances at the two base nodes, and techniques used to achieve full swing. Variations of full-swing complementary circuits utilizing different clamping diodes and full-swing techniques, implemented in a full-complementary BiCMOS technology, are presented. The FS-CMBL circuits demonstrate a clear advantage over the conventional npn-only, partial-swing BiCMOS circuit
{"title":"Full-swing logic circuits in a complementary BiCMOS technology","authors":"H.J. Shin","doi":"10.1109/VLSIC.1990.111109","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111109","url":null,"abstract":"It has been demonstrated that full-swing complementary MOS/bipolar logic (FS-CMBL) circuits utilizing a push-pull emitter-follower driver and base-emitter shunting to achieve full swing are potentially advantageous for scaled BiCMOS technologies. In these circuits, delay and power consumption depend on characteristics of the base-to-base clamping diode, parasitic capacitances at the two base nodes, and techniques used to achieve full swing. Variations of full-swing complementary circuits utilizing different clamping diodes and full-swing techniques, implemented in a full-complementary BiCMOS technology, are presented. The FS-CMBL circuits demonstrate a clear advantage over the conventional npn-only, partial-swing BiCMOS circuit","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132645027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111104
K. Arimoto, M. Asakura, H. Hidaka, Y. Matsuda, K. Fujishima
The authors describe a unique intelligent memory based on a distributed CDRAM (cache DRAM) architecture, which consists of three hierarchical memory sections, DRAM, SRAM, and CAM, that constitute on-chip TAG. This architecture provides a high-performance intelligent main memory and a pin compatibility with high-speed address nonmultiplexed memories (DRAM, SRAM, and pseudo-SRAM). This RAM can be fabricated by the standard CMOS DRAM process with little area penalty. The intelligent CDRAM with an automatic write-back function can realize a short average read/write cycle time. The write-back operation without a complex controller minimizes the write cycle time drastically compared with write through
{"title":"A circuit design of intelligent CDRAM with automatic write back capability","authors":"K. Arimoto, M. Asakura, H. Hidaka, Y. Matsuda, K. Fujishima","doi":"10.1109/VLSIC.1990.111104","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111104","url":null,"abstract":"The authors describe a unique intelligent memory based on a distributed CDRAM (cache DRAM) architecture, which consists of three hierarchical memory sections, DRAM, SRAM, and CAM, that constitute on-chip TAG. This architecture provides a high-performance intelligent main memory and a pin compatibility with high-speed address nonmultiplexed memories (DRAM, SRAM, and pseudo-SRAM). This RAM can be fabricated by the standard CMOS DRAM process with little area penalty. The intelligent CDRAM with an automatic write-back function can realize a short average read/write cycle time. The write-back operation without a complex controller minimizes the write cycle time drastically compared with write through","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125661440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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