Koji Fukuda, G. Ono, K. Watanabe, T. Muto, H. Yamashita, N. Masuda, R. Nemoto, Eiichi Suzuki, T. Takemoto, F. Yuki, M. Yagyu, H. Toyoda, M. Kono, Akihiro Kambe, Seiichi Umai, T. Saito, S. Nishimura
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引用次数: 2
Abstract
The world's first CMOS "gearbox LSI" based on 65-nm CMOS technology-namely, a 2-W 100-gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer-was developed. Its power consumption is 75% lower than that of a conventional SiGe-based gearbox LSI. The power consumption of its 12.5-Gb/s interface is 0.98 mW/(Gb/s), while that of its 25- Gb/s interface is 14 mW/(Gb/s).
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