HDL and design techniques analysis for FPGA & ASIC synthesis

Abstract

This work presents the design of a Morse decoder implemented using fourteen different architectures described in Verilog. All designs are synthesized in FPGA and ASIC, using Xilinx ISE and Vivado for the former and Leonardo Spectrum and Design Compiler for the latter. The performance and resource requirements after synthesis of each architecture are compared to gain insight on the impact caused by using different design styles, description techniques, architectural variants and the circuit’s final target.