{"title":"A digital cardiotachometer ASIC","authors":"M. Burke, A. Boilson","doi":"10.1109/ICECS.1996.584608","DOIUrl":null,"url":null,"abstract":"A circuit has been designed which measures the beat-to-beat heart-rate in humans, accepting as input a digital signal representing the subject's pulse. The range of heart-rate covered is 30-255 beats/min. The design is based on an inverse-time counter implemented using a pair of 8-bit down-counters and the associated state determining combinational logic. It also incorporates the logic for a latched 3-digit LCD decoder/driver interface in addition to an 8-bit binary output. The IC has been designed for full testability with bidirectional access to key timing and control points being provided and a scan path strategy applied to the main blocks of the chip. Various test and access modes are controlled using a decoding/multiplexing principle. The IC was designed using the 2.4 /spl mu/m CMOS Mietec cell library and Cadence EDGE software. It contains 13,000 transistors and occupies a silicon area of 25 mm/sup 2/.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.1996.584608","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A circuit has been designed which measures the beat-to-beat heart-rate in humans, accepting as input a digital signal representing the subject's pulse. The range of heart-rate covered is 30-255 beats/min. The design is based on an inverse-time counter implemented using a pair of 8-bit down-counters and the associated state determining combinational logic. It also incorporates the logic for a latched 3-digit LCD decoder/driver interface in addition to an 8-bit binary output. The IC has been designed for full testability with bidirectional access to key timing and control points being provided and a scan path strategy applied to the main blocks of the chip. Various test and access modes are controlled using a decoding/multiplexing principle. The IC was designed using the 2.4 /spl mu/m CMOS Mietec cell library and Cadence EDGE software. It contains 13,000 transistors and occupies a silicon area of 25 mm/sup 2/.
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