An energy-efficient 32-bit RISC processor for sensor platform in 90nm technology

Abstract

Due to limited life-time of battery, the energy constrained system for sensor platform has drawn a strong interest for ultra-low power research in recent years. In this paper, an energy efficient 32-bit RISC processor is discussed. The design is targeted for branch and data intensive computations. The design includes both architectural and circuit techniques to optimize energy consumption. An advance branch technique is introduced to reduce stalls in branch intensive application, which in turn decreases energy wastage due to incorrect branch decision. Architectural innovation also includes low power data memory access policy. On the circuit front, energy consumption is minimized by scaling down the supply voltage near to threshold. The 24Kb memory incorporates subthreshold 6T SRAM cell to ensure read stability at subthreshold voltage down to 0.18V. The design consumes 562pJ/instruction at optimal core and memory supply 0.5V and 0.33V respectively, for operating frequency 650KHz in 90nm technology.