Optimized Design of 4H-SiC VDMOSFET for Low ON-resistance

Abstract

In this work, we develop an optimized VDMOSFET cell structure based on 4H-SiC material. In the optimized structure, two high n-doped regions are added at both sides of the JFET region. Simulation results reveal that the additional n-doped regions not only effectively limit the depletion width in JFET region at ON-state, but also could protect the oxide layer at OFF-state due to depletion expansion. As a result, the optimized structure reduces the specific ON-resistance by 18% while keeping breakdown voltage as roughly high as the conventional structure; meanwhile, the value of figure of merit increases by 22%, which exhibits a significant improvement in device performance.