{"title":"Comparing performance metrics of a parallel ECC architecture vs. input data patterns and granularity","authors":"Esmaeil Amini, Z. Jeddi, S. Farah, M. Bayoumi","doi":"10.1109/ICEAC.2012.6471015","DOIUrl":null,"url":null,"abstract":"In this paper, we first introduce a parallel Elliptic Curve Cryptography (ECC) architecture that performs the operations required for ECC scalar point multiplication on GF(2m) operands and then we analyze the performance metrics of the architecture. The architecture is modular, can handle various operands sizes. The architecture performs several different operations in parallel when each operation requires small key size and uses power gating technique to deactivate the unutilized modules to save power. An exhaustive simulation-based study of the different performance aspect of architecture is provided considering the input data patterns, the granularity of the system and the parallelism level of the architecture.","PeriodicalId":436221,"journal":{"name":"2012 International Conference on Energy Aware Computing","volume":"112 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Conference on Energy Aware Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEAC.2012.6471015","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, we first introduce a parallel Elliptic Curve Cryptography (ECC) architecture that performs the operations required for ECC scalar point multiplication on GF(2m) operands and then we analyze the performance metrics of the architecture. The architecture is modular, can handle various operands sizes. The architecture performs several different operations in parallel when each operation requires small key size and uses power gating technique to deactivate the unutilized modules to save power. An exhaustive simulation-based study of the different performance aspect of architecture is provided considering the input data patterns, the granularity of the system and the parallelism level of the architecture.