A CMOS oversampled closed-loop DAC with embedded filtering

Abstract

A closed-loop oversampled DAC with embedded reconstruction filtering has been integrated in 0.18-μm CMOS. The architecture provides multi-bit conversion without DEM and 3rd-order filtering of out-of-band noise. At a sampling rate of 10MHz with an OSR of 16, the DAC achieves 61-dB SNDR, 63-dB DR, and 50-dB out-of-band noise suppression, while dissipating 22mW from a 1.2-V supply.