Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691002
Xin Liu, Jun Zhou, Yongkui Yang, Bo Wang, Jingjing Lan, Chao Wang, Jianwen Luo, W. Goh, T. T. Kim, M. Je
In this paper, a multi-functional ECG signal processor for wearable and implantable real-time monitoring is presented. To enable extremely long-term ambulatory monitoring, several power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An on-chip low-complexity cardiac signal analysis module is proposed to realize comprehensive analysis functions. Near-threshold circuit technique is applied to the overall system. Implemented in 0.18 μm CMOS, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V supply for real-time ambulatory monitoring. Compared with existing designs, the presented ECG processor achieves the lowest power consumption.
{"title":"A 457-nW cognitive multi-functional ECG processor","authors":"Xin Liu, Jun Zhou, Yongkui Yang, Bo Wang, Jingjing Lan, Chao Wang, Jianwen Luo, W. Goh, T. T. Kim, M. Je","doi":"10.1109/ASSCC.2013.6691002","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691002","url":null,"abstract":"In this paper, a multi-functional ECG signal processor for wearable and implantable real-time monitoring is presented. To enable extremely long-term ambulatory monitoring, several power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An on-chip low-complexity cardiac signal analysis module is proposed to realize comprehensive analysis functions. Near-threshold circuit technique is applied to the overall system. Implemented in 0.18 μm CMOS, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V supply for real-time ambulatory monitoring. Compared with existing designs, the presented ECG processor achieves the lowest power consumption.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127113280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691069
K. Katayama, M. Motoyoshi, K. Takano, L. Yang, M. Fujishima
CMOS millimeter-wave transceivers have realized over 10Gbps communication for proximity communication within 10cm distance. To increase the communication distance for indoor applications, the output power of transmitters should be increased. However, it has been difficult to simultaneously realize high power efficiency together with low power consumption and the wideband required for 10Gbps communication in the power amplifiers used in transmitters. To realize 10Gbps communication for indoor applications with CMOS technology, the co-design of a modulator with low impedance variation and a wideband power amplifier is proposed by adopting amplitude-shift keying. The proposed transceiver is fabricated using a 40nm CMOS process, and is the first transceiver to realize 11Gbps with a communication distance of 3m and has a power consumption of 208.9mW. The transmitter realized maximum 2.8dBm output power with 77mW power consumption using a power amplifier with a 3dB bandwidth of 18GHz.
{"title":"209mW 11Gbps 130GHz CMOS transceiver for indoor wireless communication","authors":"K. Katayama, M. Motoyoshi, K. Takano, L. Yang, M. Fujishima","doi":"10.1109/ASSCC.2013.6691069","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691069","url":null,"abstract":"CMOS millimeter-wave transceivers have realized over 10Gbps communication for proximity communication within 10cm distance. To increase the communication distance for indoor applications, the output power of transmitters should be increased. However, it has been difficult to simultaneously realize high power efficiency together with low power consumption and the wideband required for 10Gbps communication in the power amplifiers used in transmitters. To realize 10Gbps communication for indoor applications with CMOS technology, the co-design of a modulator with low impedance variation and a wideband power amplifier is proposed by adopting amplitude-shift keying. The proposed transceiver is fabricated using a 40nm CMOS process, and is the first transceiver to realize 11Gbps with a communication distance of 3m and has a power consumption of 208.9mW. The transmitter realized maximum 2.8dBm output power with 77mW power consumption using a power amplifier with a 3dB bandwidth of 18GHz.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115098161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691052
Sangwoo Han, Taejin Kim, Jongsun Kim
An all-digital, wide-range phase inversion delay-locked loop (PIDLL) with a high-resolution duty-cycle corrector (DCC) is presented. The proposed PIDLL utilizes a new phase inversion scheme to reduce the total number of delay elements (DEs) in the digitally controlled delay line (DCDL) by approximately one-half, enabling shorter locking times, lower power consumption, reduced jitter performance, and a smaller area, while maintaining a wide operating frequency range. To achieve high delay resolution and linear delay characteristics, a three-stage DCDL using a new area-efficient digital feedback delay element (FDE) is proposed. The FDE is also utilized to implement a new DCC that obtains a duty-cycle error of less than ±0.85% over a 30-70% input duty-cycle range. The proposed DCC-equipped PIDLL is implemented in a 0.13-μm CMOS process, occupies an area of 0.11 mm2, and operates over a wide frequency range of 0.1-1.5 GHz. It dissipates power of 5.9 mW from a 1.2 V supply at 1 GHz and exhibits a peak-to-peak output clock jitter of 11.25 ps at 1.5 GHz.
{"title":"A 0.1–1.5 GHz all-digital phase inversion delay-locked loop","authors":"Sangwoo Han, Taejin Kim, Jongsun Kim","doi":"10.1109/ASSCC.2013.6691052","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691052","url":null,"abstract":"An all-digital, wide-range phase inversion delay-locked loop (PIDLL) with a high-resolution duty-cycle corrector (DCC) is presented. The proposed PIDLL utilizes a new phase inversion scheme to reduce the total number of delay elements (DEs) in the digitally controlled delay line (DCDL) by approximately one-half, enabling shorter locking times, lower power consumption, reduced jitter performance, and a smaller area, while maintaining a wide operating frequency range. To achieve high delay resolution and linear delay characteristics, a three-stage DCDL using a new area-efficient digital feedback delay element (FDE) is proposed. The FDE is also utilized to implement a new DCC that obtains a duty-cycle error of less than ±0.85% over a 30-70% input duty-cycle range. The proposed DCC-equipped PIDLL is implemented in a 0.13-μm CMOS process, occupies an area of 0.11 mm2, and operates over a wide frequency range of 0.1-1.5 GHz. It dissipates power of 5.9 mW from a 1.2 V supply at 1 GHz and exhibits a peak-to-peak output clock jitter of 11.25 ps at 1.5 GHz.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122482565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691048
Qixian Shi, K. Vaesen, B. Parvais, G. Mangraviti, P. Wambacq
This paper presents a 40nm CMOS transformer-based dual-band VCO with differential hybrid coupler for I/Q generation. The average phase noise of the combination over the 54 to 69.3GHz tuning range is -90dBc/Hz at 1MHz offset while the best FOM value is 177dB. Along the wide tuning range from 54 to 67GHz, the I/Q mismatch of the hybrid coupler is less than 3°. The area of the hybrid is only 60μm-65μm.
{"title":"A 54–69.3 GHz dual-band VCO with differential hybrid coupler for quadrature generation","authors":"Qixian Shi, K. Vaesen, B. Parvais, G. Mangraviti, P. Wambacq","doi":"10.1109/ASSCC.2013.6691048","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691048","url":null,"abstract":"This paper presents a 40nm CMOS transformer-based dual-band VCO with differential hybrid coupler for I/Q generation. The average phase noise of the combination over the 54 to 69.3GHz tuning range is -90dBc/Hz at 1MHz offset while the best FOM value is 177dB. Along the wide tuning range from 54 to 67GHz, the I/Q mismatch of the hybrid coupler is less than 3°. The area of the hybrid is only 60μm-65μm.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117090961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691015
Y. Shih, Hong-Lin Chu, Wei-Kai Hong, Chao-Ching Hung, A. Tanzil, Y. Huang, Jun-Yu Chen, Li-Han Hung, Lan-chou Cho, Junmin Cao, Yen-Chuan Huang, Y. Hsueh, Y. Chung
This paper describes a 55nm, 0.6mm2 Bluetooth SoC integrated in cellular baseband. Several techniques are used to enhance co-existence performance of Bluetooth with cellular and Wi-Fi. First is the design of current-mode interfaces from LNA to complex BPF for better linearity and the additional antialiasing LPF placed before ADC for outband rejection in the RX. Second is the use of a passive voltage sampling mixer to lower out-of-band emission noise floor in TX. Moreover, only two inductors are used, one of which is a field-cancelling inductor used in VCO layout to achieve a spur-free LO signal, minimizing magnetic coupling from other parts of SoC. The TX output power is +11dBm at BDR mode and +8dBm at EDR3 mode, with 1.5-kHz frequency drift and <;6% RMS DEVM. The RX sensitivity is better than -96.5dBm and -89.2dBm for BDR and EDR3 modes respectively. The measured BT RX sensitivity is -57dBm at BDR mode while co-existing with -5dBm of Wi-Fi 54Mbps OFDM.
{"title":"A 55nm, 0.6mm2 Bluetooth SoC integrated in cellular baseband chip with enhanced coexistence","authors":"Y. Shih, Hong-Lin Chu, Wei-Kai Hong, Chao-Ching Hung, A. Tanzil, Y. Huang, Jun-Yu Chen, Li-Han Hung, Lan-chou Cho, Junmin Cao, Yen-Chuan Huang, Y. Hsueh, Y. Chung","doi":"10.1109/ASSCC.2013.6691015","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691015","url":null,"abstract":"This paper describes a 55nm, 0.6mm2 Bluetooth SoC integrated in cellular baseband. Several techniques are used to enhance co-existence performance of Bluetooth with cellular and Wi-Fi. First is the design of current-mode interfaces from LNA to complex BPF for better linearity and the additional antialiasing LPF placed before ADC for outband rejection in the RX. Second is the use of a passive voltage sampling mixer to lower out-of-band emission noise floor in TX. Moreover, only two inductors are used, one of which is a field-cancelling inductor used in VCO layout to achieve a spur-free LO signal, minimizing magnetic coupling from other parts of SoC. The TX output power is +11dBm at BDR mode and +8dBm at EDR3 mode, with 1.5-kHz frequency drift and <;6% RMS DEVM. The RX sensitivity is better than -96.5dBm and -89.2dBm for BDR and EDR3 modes respectively. The measured BT RX sensitivity is -57dBm at BDR mode while co-existing with -5dBm of Wi-Fi 54Mbps OFDM.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128466889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690969
Hyun-Kyu Yu
Rapid industry reform from desktop era to mobile computing has led to the widespread adoption of application processors throughout the IT industry. While the application processor market has become mainstream in recent years, it is still struggling for more performance while maintaining portability in several areas such as computer vision and mixed-reality. The semiconductor industry looks to satisfy these market requirements with many-core hand-top supercomputing. The emergence of many-core computing as the next step in the progression of the industry presents several design challenges for system architects: reasonable power consumption, software programming, core reliability, and core utilization for scalable performance. We review current developments of application processor SoCs and give a forecast for future many-core the SW-SoC platform.
{"title":"Reliable hand-top many-core SW-SoC platform","authors":"Hyun-Kyu Yu","doi":"10.1109/ASSCC.2013.6690969","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690969","url":null,"abstract":"Rapid industry reform from desktop era to mobile computing has led to the widespread adoption of application processors throughout the IT industry. While the application processor market has become mainstream in recent years, it is still struggling for more performance while maintaining portability in several areas such as computer vision and mixed-reality. The semiconductor industry looks to satisfy these market requirements with many-core hand-top supercomputing. The emergence of many-core computing as the next step in the progression of the industry presents several design challenges for system architects: reasonable power consumption, software programming, core reliability, and core utilization for scalable performance. We review current developments of application processor SoCs and give a forecast for future many-core the SW-SoC platform.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128599911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691053
T. Nakura, K. Asada
This paper demonstrates pulse width controlled PLL and DLL using a soft thermometer code. The oscillation frequency control in the PLL and the delay control in the DLL are conducted by a mostly digital with one bit analog code. Both of our PLL/DLL do not use an area-consuming capacitor, resulting in small silicon area implementation. A 65nm CMOS process uses only 120μm×30μm area for the PLL+DLL. They realized 2.80GHz operation consuming 1.35mW/4.65mW with 1.60ps/1.78ps rms jitter from the PLL/DLL output signals.
{"title":"Pulse width controlled PLL/DLL using soft thermometer code","authors":"T. Nakura, K. Asada","doi":"10.1109/ASSCC.2013.6691053","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691053","url":null,"abstract":"This paper demonstrates pulse width controlled PLL and DLL using a soft thermometer code. The oscillation frequency control in the PLL and the delay control in the DLL are conducted by a mostly digital with one bit analog code. Both of our PLL/DLL do not use an area-consuming capacitor, resulting in small silicon area implementation. A 65nm CMOS process uses only 120μm×30μm area for the PLL+DLL. They realized 2.80GHz operation consuming 1.35mW/4.65mW with 1.60ps/1.78ps rms jitter from the PLL/DLL output signals.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124546190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691049
Nam-Seog Kim, J. Rabaey
A wide lock-range supply regulated integer-N QPLL is proposed to reduce power consumption of the wideband direct digital RF modulator. SINC roll-off characteristic for supply noise of the inverter-based ring-VCOs in frequency domain maximizes loop bandwidth of the wide lock-range PLL. The proposed charge pump keeps loop bandwidth for all integer-N divider ratio. The fabricated QPLL achieves 0.2 to 1.7GHz lock rage with 10MHz bandwidth, 100MHz reference, and on-chip loop filter. The RMS jitter is 1.28ps, maximum supply noise sensitivity is 0.34rad/V, and power consumption is 13.2mW from 1V supply at 1.7GHz PLL output frequency. The active area is 0.064mm2.
{"title":"A 0.2 to 1.7 GHz low-jitter integer-N QPLL for power efficient direct digital RF modulator","authors":"Nam-Seog Kim, J. Rabaey","doi":"10.1109/ASSCC.2013.6691049","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691049","url":null,"abstract":"A wide lock-range supply regulated integer-N QPLL is proposed to reduce power consumption of the wideband direct digital RF modulator. SINC roll-off characteristic for supply noise of the inverter-based ring-VCOs in frequency domain maximizes loop bandwidth of the wide lock-range PLL. The proposed charge pump keeps loop bandwidth for all integer-N divider ratio. The fabricated QPLL achieves 0.2 to 1.7GHz lock rage with 10MHz bandwidth, 100MHz reference, and on-chip loop filter. The RMS jitter is 1.28ps, maximum supply noise sensitivity is 0.34rad/V, and power consumption is 13.2mW from 1V supply at 1.7GHz PLL output frequency. The active area is 0.064mm2.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"45 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120926239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690989
Wai Pan Chan, Arup K. George, M. Narducci, D. D. Cheam, S. C. Leong, M. Tsai, A. A. Rahman, M. K. Park, Z. Kong, J. Rao, Yuan Gao, M. Je
A fully integrated SoC for multimodality intracranial neuromonitoring is presented. This SoC includes a capacitive MEMS pressure sensor, an electrochemical oxygen sensor, a solid-state temperature sensor and sensor interface circuits in a single chip. Chopper stabilization and dynamic element matching techniques are applied in sensor interface circuits to reduce circuit noise and offset. On-chip calibration is implemented for each sensor to compensate process variations. Measured accuracies of the pressure, oxygen, and temperature sensors are ±1 mmHg, ±1 mmHg, and ±0.2 oC, respectively. Implemented in 0.18-μm CMOS, the SoC occupies an area of 1.4 mm × 4mm and consumes 188-μW DC power.
提出了一种完全集成的多模态颅内神经监测SoC。该SoC包括电容式MEMS压力传感器，电化学氧传感器，固态温度传感器和单个芯片中的传感器接口电路。在传感器接口电路中采用斩波稳定技术和动态元件匹配技术来降低电路噪声和失调。对每个传感器进行片上校准，以补偿工艺变化。压力传感器、氧气传感器和温度传感器的测量精度分别为±1mmhg、±1mmhg和±0.2 oC。该SoC采用0.18 μm CMOS，面积为1.4 mm × 4mm，直流功耗为188 μ w。
{"title":"A pressure/oxygen/temperature sensing SoC for multimodality intracranial neuromonitoring","authors":"Wai Pan Chan, Arup K. George, M. Narducci, D. D. Cheam, S. C. Leong, M. Tsai, A. A. Rahman, M. K. Park, Z. Kong, J. Rao, Yuan Gao, M. Je","doi":"10.1109/ASSCC.2013.6690989","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690989","url":null,"abstract":"A fully integrated SoC for multimodality intracranial neuromonitoring is presented. This SoC includes a capacitive MEMS pressure sensor, an electrochemical oxygen sensor, a solid-state temperature sensor and sensor interface circuits in a single chip. Chopper stabilization and dynamic element matching techniques are applied in sensor interface circuits to reduce circuit noise and offset. On-chip calibration is implemented for each sensor to compensate process variations. Measured accuracies of the pressure, oxygen, and temperature sensors are ±1 mmHg, ±1 mmHg, and ±0.2 oC, respectively. Implemented in 0.18-μm CMOS, the SoC occupies an area of 1.4 mm × 4mm and consumes 188-μW DC power.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"178 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116283296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691075
Xuan Zhang, D. Brooks, Gu-Yeon Wei
Efficient actuation control of flapping-wing microrobots requires a low-power frequency reference with good absolute accuracy. To meet this requirement, we designed a fully-integrated 10MHz relaxation oscillator in a 40nm CMOS process. By adaptively biasing the continuous-time comparator, we are able to achieve a power consumption of 20μW, a 68% reduction to the conventional fixed bias design. A built-in self-calibration controller enables fast post-fabrication calibration of the clock frequency. Measurements show a frequency drift of 1.2% as the battery voltage changes from 3V to 4.1V.
{"title":"A 20μW 10MHz relaxation oscillator with adaptive bias and fast self-calibration in 40nm CMOS for micro-aerial robotics application","authors":"Xuan Zhang, D. Brooks, Gu-Yeon Wei","doi":"10.1109/ASSCC.2013.6691075","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691075","url":null,"abstract":"Efficient actuation control of flapping-wing microrobots requires a low-power frequency reference with good absolute accuracy. To meet this requirement, we designed a fully-integrated 10MHz relaxation oscillator in a 40nm CMOS process. By adaptively biasing the continuous-time comparator, we are able to achieve a power consumption of 20μW, a 68% reduction to the conventional fixed bias design. A built-in self-calibration controller enables fast post-fabrication calibration of the clock frequency. Measurements show a frequency drift of 1.2% as the battery voltage changes from 3V to 4.1V.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"27 25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121561374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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