Development of advanced fan-out wafer level package (embedded wafer level BGA)

Abstract

With reducing of silicon techno, the pitches and pads at the chip to package interface become important factor. This drives interconnection toward to fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. Fan-out WLP has the potential to realize any number of interconnects at any shrink stage of the wafer node technology.