Discussion on the low-power CMOS latches and flip-flops

Abstract

Latches and flip-flops used in low power circuits are discussed in this paper. Two kinds of latches of 5-T and 4-T are evolved from the standard 8-T static latch for low power application. Simulation results show that the 4-T latch has the lowest power consumption with no speed penalty. The 4-T latch is usually considered as dynamic. However, detailed analysis shows that it may be static under certain conditions, which are also given in this paper. Single-edge-trigged (SET) flip-flops and double-edge-trigged (DET) flip-flop based on these latches are also presented. Significant power and area savings can achieve by using 4-T latches.