Process characterization for strained Si on SOI CMOS devices

Abstract

Although the strained-Si channel engineering seems to be rather compatible with the existing mainstream CMOS process, the use of strained Si on SOI virtual substrates introduces new process and integration issues that need to be addressed for successful manufacturability and reliability. Even for ideal strained Si on SOI substrates, the impacts of various CMOS process steps, e.g., patterning, oxidation, implantation and annealing, on strain relaxation, defect formation and Ge interdiffusion need to be well understood and controlled before feasible process integration can be achieved. In this work, we investigate the influences of pad oxidation, gate oxidation and dopant-activation annealling on strained Si on SOI heterostructures by using UV micro-Raman spectroscopy in combination with other characterization techniques, such as Auger electron spectroscopy (AES), atomic force microscopy (AFM), high resolution x-ray diffraction (HRXRD), secondary ion mass spectrometry (SIMS), transmission electron microscopy (TEM).