Process Variation-Aware Analytical Modeling of Subthreshold Leakage Power

Abstract

Leakage current is making a substantial contribution to the power dissipation in nanometer regime due to continued technology scaling. The problem is further accentuated with the increasing levels of unpredictability in process parameters. Consequently, accurate and reliable modeling of leakage current is critical for the prediction of static power, especially for ultra low power applications. In contrast to gate leakage and Band-to-Band-Tunneling (BTBT) leakage, subthreshold leakage is the most sensitive to parameter variations and hence has been considered for variability modeling. The variations in electrical and geometry parameters of the device drastically impact the sub-threshold leakage current. In this paper, a subthreshold leakage power estimation model in the presence of process variations, with Drain-Induced Barrier Lowering (DIBL) considerations, is proposed. The model focuses on the subthreshold leakage variations induced by the simultaneous effect of threshold voltage variability and variations in gate length and width. The variation in the subthreshold leakage power is characterized by using an extensive Monte Carlo analysis. In order to demonstrate the efficacy of the proposed model, the model generated distributions of a static CMOS inverter are overlaid on the SPICE generated distributions in 32 nm PTM technology. The results demonstrate that, in the presence of process variations, the proposed model offers better predictability with a mean error in the range of 0.09% to 0.45% and reduction in the standard deviation of 3.3% to 34%, resulting in tighter distributions, thereby ensuring better predictability and design robustness. Further, the proposed model is about 700X computationally faster than SPICE simulations.