Pei-Shi Yu, Guangming Tang, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun
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引用次数: 2
Abstract
An 8-bit bit-slice TEA-cryptographic accelerator for 64-bit RSFQ secure coprocessors is proposed. The accelerator is based on Tiny Encryption Algorithm (TEA) and mainly consists of bit-slice adders and bit-slice shifters. Synchronous concurrent-flow clocking is used to design a fully pipelined RSFQ logic design. For verifying the algorithm and the logic design, the RSFQ logic circuits of the proposed accelerator have been simulated with a target operating frequency of 50 GHz. It consists of 21 stages. The throughput is 7.672 × 107 64-bit TEA encryptions per second.
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