Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990902
Pei-Shi Yu, Guangming Tang, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun
An 8-bit bit-slice TEA-cryptographic accelerator for 64-bit RSFQ secure coprocessors is proposed. The accelerator is based on Tiny Encryption Algorithm (TEA) and mainly consists of bit-slice adders and bit-slice shifters. Synchronous concurrent-flow clocking is used to design a fully pipelined RSFQ logic design. For verifying the algorithm and the logic design, the RSFQ logic circuits of the proposed accelerator have been simulated with a target operating frequency of 50 GHz. It consists of 21 stages. The throughput is 7.672 × 107 64-bit TEA encryptions per second.
{"title":"An 8-bit Bit-Slice TEA-Cryptographic Accelerator for 64-bit RSFQ Secure Coprocessors","authors":"Pei-Shi Yu, Guangming Tang, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun","doi":"10.1109/ISEC46533.2019.8990902","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990902","url":null,"abstract":"An 8-bit bit-slice TEA-cryptographic accelerator for 64-bit RSFQ secure coprocessors is proposed. The accelerator is based on Tiny Encryption Algorithm (TEA) and mainly consists of bit-slice adders and bit-slice shifters. Synchronous concurrent-flow clocking is used to design a fully pipelined RSFQ logic design. For verifying the algorithm and the logic design, the RSFQ logic circuits of the proposed accelerator have been simulated with a target operating frequency of 50 GHz. It consists of 21 stages. The throughput is 7.672 × 107 64-bit TEA encryptions per second.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"193 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116784320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990905
Ikki Nagaoka, Masamitsu Tanaka, K. Sano, T. Yamashita, A. Fujimaki, Koji Inoue
We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm2 Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).
{"title":"Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic","authors":"Ikki Nagaoka, Masamitsu Tanaka, K. Sano, T. Yamashita, A. Fujimaki, Koji Inoue","doi":"10.1109/ISEC46533.2019.8990905","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990905","url":null,"abstract":"We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm2 Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125135336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990947
Hao Li, Han Cai, E. Cho, Yan-Ting Wang, S. Cybart
We successfully fabricated high-transition temperature $(mathrm{high}-T_{C})$ nano-scale superconducting quantum interference devices (nano-SQUIDs) by using a 32-keV focused helium ion beam (FHIB). The $sim 0.5$ nm beam of the FHIB was used to disorder the crystaline lattice of YBa2Cu $3mathrm{O}_{7-delta}$ (YBCO) causing disorder that converts the material from superconductor to insulator at high dose. The SQUID loop size was 400 nm x 400 nm, with 200-nm wide Josephson junctions. Devices operated over a wide range of temperatures from 50 to 4 K and exhibited large voltage modulation with magnetic field as high as 500 $mu mathrm{V}$.
{"title":"YBa2Cu3O7-δ Nano-SQUIDs Fabricated by Focused Helium Ion Beam Direct Writing","authors":"Hao Li, Han Cai, E. Cho, Yan-Ting Wang, S. Cybart","doi":"10.1109/ISEC46533.2019.8990947","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990947","url":null,"abstract":"We successfully fabricated high-transition temperature $(mathrm{high}-T_{C})$ nano-scale superconducting quantum interference devices (nano-SQUIDs) by using a 32-keV focused helium ion beam (FHIB). The $sim 0.5$ nm beam of the FHIB was used to disorder the crystaline lattice of YBa2Cu $3mathrm{O}_{7-delta}$ (YBCO) causing disorder that converts the material from superconductor to insulator at high dose. The SQUID loop size was 400 nm x 400 nm, with 200-nm wide Josephson junctions. Devices operated over a wide range of temperatures from 50 to 4 K and exhibited large voltage modulation with magnetic field as high as 500 $mu mathrm{V}$.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129606232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990962
L. Schindler, R. van Staden, C. Fourie, C. Ayala, J. A. Coetzee, Tomoyuki Tanaka, Ro Saito, N. Yoshikawa
In this work under the IARPA SuperTools program we developed a layout synthesis tool with scripting support. The user specifies the relative positions of Josephson junctions and inductances constrained by a user-defined cell height and cell width. Tight integration with the three-dimensional inductance extraction tool, InductEx, allows inductances to be automatically generated while meeting reasonable design values. Based on these user inputs, the tool can synthesize the physical layout of logic cells for multiple SFQ circuit technologies according to design rules and layer parameters. Furthermore, it enables the straightforward regeneration of entire cell libraries when design rules change or when libraries have to be redesigned for more advanced fabrication processes. We describe the methodology of our synthesis tool and show the results applied to both RSFQ and AQFP logic families.
{"title":"Standard Cell Layout Synthesis for Row-Based Placement and Routing of RSFQ and AQFP Logic Families","authors":"L. Schindler, R. van Staden, C. Fourie, C. Ayala, J. A. Coetzee, Tomoyuki Tanaka, Ro Saito, N. Yoshikawa","doi":"10.1109/ISEC46533.2019.8990962","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990962","url":null,"abstract":"In this work under the IARPA SuperTools program we developed a layout synthesis tool with scripting support. The user specifies the relative positions of Josephson junctions and inductances constrained by a user-defined cell height and cell width. Tight integration with the three-dimensional inductance extraction tool, InductEx, allows inductances to be automatically generated while meeting reasonable design values. Based on these user inputs, the tool can synthesize the physical layout of logic cells for multiple SFQ circuit technologies according to design rules and layer parameters. Furthermore, it enables the straightforward regeneration of entire cell libraries when design rules change or when libraries have to be redesigned for more advanced fabrication processes. We describe the methodology of our synthesis tool and show the results applied to both RSFQ and AQFP logic families.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129608311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990963
Kyle Jackman, C. Fourie
Several advances have been made towards increasing the number of Niobium layers for superconductor integrated circuits. Fabrication processes, such as the MIT Lincoln Laboratory SFQ5ee process and the CRAVITY-AIST process, now provide eight or more Niobium layers. The additional superconducting layers significantly increase the space available for routing between and within cells. However, striplines must now be routed through multiple ground planes to efficiently utilize all available metal layers. This can lead to large mutual inductance between signal lines, especially when ground pillars are used to connect ground planes. The placement of these ground pillars become crucial. In this work, we use numerical software to analyze the effects of striplines transitioning through multiple ground planes and how the location of ground pillars influence the mutual inductance between lines and show that careful layout considerations are required for modern circuits with dense layouts. We also present layout improvement strategies to mitigate or lessen the negative effects of these mutual inductance on circuit operation.
{"title":"Layout Strategies for Connecting Multiple Superconducting Ground Planes with Ground Pillars","authors":"Kyle Jackman, C. Fourie","doi":"10.1109/ISEC46533.2019.8990963","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990963","url":null,"abstract":"Several advances have been made towards increasing the number of Niobium layers for superconductor integrated circuits. Fabrication processes, such as the MIT Lincoln Laboratory SFQ5ee process and the CRAVITY-AIST process, now provide eight or more Niobium layers. The additional superconducting layers significantly increase the space available for routing between and within cells. However, striplines must now be routed through multiple ground planes to efficiently utilize all available metal layers. This can lead to large mutual inductance between signal lines, especially when ground pillars are used to connect ground planes. The placement of these ground pillars become crucial. In this work, we use numerical software to analyze the effects of striplines transitioning through multiple ground planes and how the location of ground pillars influence the mutual inductance between lines and show that careful layout considerations are required for modern circuits with dense layouts. We also present layout improvement strategies to mitigate or lessen the negative effects of these mutual inductance on circuit operation.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121530368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990913
M. Krantz, A. Fleischmann, C. Enss, S. Kempf
Metallic magnetic calorimeters are energy-dispersive cryogenic particle detectors providing an excellent energy resolution, a fast signal rise time, a high quantum efficiency as well as an almost ideal linear detector response. To surpass the present record resolution of 1.6 eV (FWHM) for 6 keV photons, we have started to develop integrated detectors for which the paramagnetic temperature sensor monitoring the temperature rise of the detector is integrated directly into the pickup loop of the superconducting quantum interference device. Due to the greatly enhanced magnetic flux coupling and consequently the reduced contribution of SQUID noise to the overall noise spectrum, this kind of devices should push the resolution to a value well below 1 eV. Here, we discuss the design and performance of a prototype 64 pixels metallic magnetic calorimeter based detector array with integrated detectors that rely on first-order parallel gradiometric SQUIDs with two meander-shaped pickup coils onto which planar temperature sensor made of Ag:Er are deposited.
金属磁量热计是能量色散低温粒子探测器，具有优异的能量分辨率，快速的信号上升时间，高量子效率以及几乎理想的线性探测器响应。为了超越目前记录的6 keV光子的1.6 eV (FWHM)分辨率，我们已经开始开发集成探测器，将监测探测器温升的顺磁温度传感器直接集成到超导量子干涉器件的拾取回路中。由于磁通量耦合大大增强，从而降低了SQUID噪声对整体噪声谱的贡献，这种器件应将分辨率推至远低于1 eV的值。在这里，我们讨论了基于64像素金属磁量热计的探测器阵列的原型设计和性能，该阵列具有集成探测器，依赖于具有两个弯曲形状拾取线圈的一阶平行梯度squid，其上沉积了由Ag:Er制成的平面温度传感器。
{"title":"Towards Energy-Dispersive Particle Detection with sub-eV Energy Resolution: Metallic Magnetic Calorimeters with Direct Sensor Readout","authors":"M. Krantz, A. Fleischmann, C. Enss, S. Kempf","doi":"10.1109/ISEC46533.2019.8990913","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990913","url":null,"abstract":"Metallic magnetic calorimeters are energy-dispersive cryogenic particle detectors providing an excellent energy resolution, a fast signal rise time, a high quantum efficiency as well as an almost ideal linear detector response. To surpass the present record resolution of 1.6 eV (FWHM) for 6 keV photons, we have started to develop integrated detectors for which the paramagnetic temperature sensor monitoring the temperature rise of the detector is integrated directly into the pickup loop of the superconducting quantum interference device. Due to the greatly enhanced magnetic flux coupling and consequently the reduced contribution of SQUID noise to the overall noise spectrum, this kind of devices should push the resolution to a value well below 1 eV. Here, we discuss the design and performance of a prototype 64 pixels metallic magnetic calorimeter based detector array with integrated detectors that rely on first-order parallel gradiometric SQUIDs with two meander-shaped pickup coils onto which planar temperature sensor made of Ag:Er are deposited.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128058908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990894
A. Fayyazi, Shahin Nazarian, M. Pedram
Superconducting devices have emerged as one of the most promising beyond-CMOS technologies with a switching delay of 1ps and switching energy of $10^{-19}mathrm{J}$ to achieve high performance, energy-efficient systems and make quantum computing a reality. Design and verification methodologies of single flux quantum (SFQ) logic fundamentally differ from those of the CMOS logic, due to key differences such as pulse signal type, ultra-deep (gate-level) pipelining, and path-balancing in SFQ circuits. In this paper, we propose a framework for logical equivalence checking (LEC) of SFQ circuits called qEC. qEC is built on the ABC tool however with the ability to check on properties of SFQ superconducting circuits. Several timing and structural checks are embedded in our framework. We benchmark the framework on post-synthesis netlists with an SFQ technology. Results show a comparative verification time of Sport lab SFQ logic circuit benchmark suite including 16-bit Array multiplier, 16-bit integer divider and ISCAS'85 circuits with respect to ABC tool for similar CMOS circuits.
{"title":"qEC: A Logical Equivalence Checking Framework Targeting SFQ Superconducting Circuits","authors":"A. Fayyazi, Shahin Nazarian, M. Pedram","doi":"10.1109/ISEC46533.2019.8990894","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990894","url":null,"abstract":"Superconducting devices have emerged as one of the most promising beyond-CMOS technologies with a switching delay of 1ps and switching energy of $10^{-19}mathrm{J}$ to achieve high performance, energy-efficient systems and make quantum computing a reality. Design and verification methodologies of single flux quantum (SFQ) logic fundamentally differ from those of the CMOS logic, due to key differences such as pulse signal type, ultra-deep (gate-level) pipelining, and path-balancing in SFQ circuits. In this paper, we propose a framework for logical equivalence checking (LEC) of SFQ circuits called qEC. qEC is built on the ABC tool however with the ability to check on properties of SFQ superconducting circuits. Several timing and structural checks are embedded in our framework. We benchmark the framework on post-synthesis netlists with an SFQ technology. Results show a comparative verification time of Sport lab SFQ logic circuit benchmark suite including 16-bit Array multiplier, 16-bit integer divider and ISCAS'85 circuits with respect to ABC tool for similar CMOS circuits.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114863391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990932
J. Son., Soon-Gul Lee, Woon Song, Y. Chong, Gahyun Choi, T. Noh, Jisoo Choi, Gwanyeol Park, Joonyoung Lee, B. Kang, Kibog Park, Kwan-Woo Lee
A transmon qubit in the 3-dimensional microwave cavity is a versatile system for various circuit QED experiments. We have performed numerical calculations of the vacuum Rabi coupling $g$ in 3D transmon circuit QED system, and compared the values with the experimental measurements. We used COMSOL Multiphysics RF package with an appropriate model to efficiently calculate the coupling strength. The calculation agrees with the measurement within a few percents in simple cases. Depending on the position of the qubit in the cavity, we calculated the coupling strengths to different eigenmodes. We compared our result for the fundamental mode (TE101) and a higher mode (TE201) with the experiment by changing the qubit position, as shown in Fig. 2. This simulation and characterization enable efficient design methods for future 3D circuit QED experiments. We confirm that we can design and predict the qubit coupling to the cavity modes with enough accuracy in 3D circuit QED system.
{"title":"Simulation and Measurement of the Vacuum Rabi Coupling g in a 3D Transmon System","authors":"J. Son., Soon-Gul Lee, Woon Song, Y. Chong, Gahyun Choi, T. Noh, Jisoo Choi, Gwanyeol Park, Joonyoung Lee, B. Kang, Kibog Park, Kwan-Woo Lee","doi":"10.1109/ISEC46533.2019.8990932","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990932","url":null,"abstract":"A transmon qubit in the 3-dimensional microwave cavity is a versatile system for various circuit QED experiments. We have performed numerical calculations of the vacuum Rabi coupling $g$ in 3D transmon circuit QED system, and compared the values with the experimental measurements. We used COMSOL Multiphysics RF package with an appropriate model to efficiently calculate the coupling strength. The calculation agrees with the measurement within a few percents in simple cases. Depending on the position of the qubit in the cavity, we calculated the coupling strengths to different eigenmodes. We compared our result for the fundamental mode (TE101) and a higher mode (TE201) with the experiment by changing the qubit position, as shown in Fig. 2. This simulation and characterization enable efficient design methods for future 3D circuit QED experiments. We confirm that we can design and predict the qubit coupling to the cavity modes with enough accuracy in 3D circuit QED system.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117210711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990955
K. Osborn, W. Wustmann
Today's industrial digital logic gates are reaching a technological limit and meanwhile, superconducting circuits produce fundamentally different technologies for the future of digital computing. The standard logic is irreversible and yet superconducting circuits allow digital reversible logic with a much higher energy efficiency per gate operation. Previous reversible gate circuits were “adiabatic,” meaning that they used adiabatic-clocking waveforms for their operation power. However, we are studying logic starting from a ballistic model, where ftuxons enable gates using only energy from their inertia. Our ftuxons are defined in Long Josephson Junctions (LJJs) and may travel ballistically, similar to a particle with negligible damping. Once a ftuxon's energy approaches close enough to the gate, a resonance is induced at the gate and the ftuxon loses its definite topology. Gates are comprised of the (few Josephson-penetration-depth long) ends of LJJs and a connecting circuit interface. Only after the resonance does a ftuxon get formed and yield the gate result without external power: a ftuxon for bit-state 0 or an antiftuxon for bit-state 1. Through earlier analysis of the numerically discovered phenomena we find that dynamics can be described with ftuxon- and antiftuxon-like excitations at the ends of LJJs within the gate. The bit-switching action in our gates is resonant indicating fundamentally different dynamics than the classic model of adiabatic reversible circuits. Our ballistic Reversible Fluxon Logic (RFL) gates have no added damping and calculated energy efficiencies of over 97%. Thus in our dynamical process the “bit energy” is preserved. However, irreversible logic completely dissipates this at each operation (e.g., charging energy in CMOS or SFQ energy in irreversible SFQ logic). An RFL gate can achieve a fast gate operation since its resonance is only few JJ plasma periods. We also describe the CNOT in our technology. It is enabled by a couple of vital gates: A IDSN logic gate, similar to our other ballistic gates, and a Store-aNd-Launch (SNL) timing gate to ensure proper synchronization of the bits. The latter allows bit storage followed by launching of a data ftuxon using an adiabatic pulse from a clock ftuxon with lower energy than the data ftuxon for good CNOT efficiency.
{"title":"Reversible Fluxon Logic for Future Computing","authors":"K. Osborn, W. Wustmann","doi":"10.1109/ISEC46533.2019.8990955","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990955","url":null,"abstract":"Today's industrial digital logic gates are reaching a technological limit and meanwhile, superconducting circuits produce fundamentally different technologies for the future of digital computing. The standard logic is irreversible and yet superconducting circuits allow digital reversible logic with a much higher energy efficiency per gate operation. Previous reversible gate circuits were “adiabatic,” meaning that they used adiabatic-clocking waveforms for their operation power. However, we are studying logic starting from a ballistic model, where ftuxons enable gates using only energy from their inertia. Our ftuxons are defined in Long Josephson Junctions (LJJs) and may travel ballistically, similar to a particle with negligible damping. Once a ftuxon's energy approaches close enough to the gate, a resonance is induced at the gate and the ftuxon loses its definite topology. Gates are comprised of the (few Josephson-penetration-depth long) ends of LJJs and a connecting circuit interface. Only after the resonance does a ftuxon get formed and yield the gate result without external power: a ftuxon for bit-state 0 or an antiftuxon for bit-state 1. Through earlier analysis of the numerically discovered phenomena we find that dynamics can be described with ftuxon- and antiftuxon-like excitations at the ends of LJJs within the gate. The bit-switching action in our gates is resonant indicating fundamentally different dynamics than the classic model of adiabatic reversible circuits. Our ballistic Reversible Fluxon Logic (RFL) gates have no added damping and calculated energy efficiencies of over 97%. Thus in our dynamical process the “bit energy” is preserved. However, irreversible logic completely dissipates this at each operation (e.g., charging energy in CMOS or SFQ energy in irreversible SFQ logic). An RFL gate can achieve a fast gate operation since its resonance is only few JJ plasma periods. We also describe the CNOT in our technology. It is enabled by a couple of vital gates: A IDSN logic gate, similar to our other ballistic gates, and a Store-aNd-Launch (SNL) timing gate to ensure proper synchronization of the bits. The latter allows bit storage followed by launching of a data ftuxon using an adiabatic pulse from a clock ftuxon with lower energy than the data ftuxon for good CNOT efficiency.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130041789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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