A 15 ns 32×32-bit CMOS multiplier with an improved parallel structure

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56842

M. Nagamatsu, Sumio Tanaka, J. Mori, T. Noguchi, K. Hatanaka

引用次数: 23

Abstract

A 32-bit×32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8-μm CMOS triple-level-metal interconnection technology. A unit adder that can sum four partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68×2.71-mm2 die area. The multiplication time is 15 ns at 5-V power supply. The power dissipation is 277 mW at 10-MHz operation

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一种改进并行结构的15 ns 32倍32位CMOS乘法器

采用0.8 μm CMOS三电平金属互连技术，制备了一种改进并联结构的32-bit×32-bit并联倍增器。研制了一种能同时对四个部分乘积求和的单位加法器。增强了乘法器的并行性。该芯片包含27704个晶体管，芯片面积为2.68×2.71-mm2。在5v电源下，乘法时间为15ns。10mhz工作时的功耗为277 mW

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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