A Highly Reliable and Cost Effective 16nm Planar NAND Cell Technology

William Kueber, G. Puzzilli, Niccolò Righetti, R. Basco, Lin Li, S. Beltrami, M. Bertuccio, E. Camozzi, David Daycock, Matthew King, Chris Larsen, Jeff Karpan, A. Goda, C. Roberts
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引用次数: 1

Abstract

A 2D 16nm planar NAND cell technology is described with good cell to cell interference and reliability that can be used in a wide variety of applications. This second generation planar cell uses a high-K dielectric stack and a thin poly floating gate to maintain the needed gate coupling ratio and reduce adjacent cell interference. The technology includes select gates with the same planar structure as the cell. This select gate architecture simplifies the manufacturing of this NAND technology.
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一种高可靠且低成本的16nm平面NAND电池技术
描述了一种二维16nm平面NAND单元技术,具有良好的单元间干扰和可靠性,可用于各种应用。这种第二代平面电池采用高k介电堆和薄聚浮栅来维持所需的栅极耦合比并减少相邻电池的干扰。该技术包括选择与单元具有相同平面结构的栅极。这种选择门架构简化了NAND技术的制造。
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