Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150291
E. Capogreco, R. Degraeve, J. Lisoni, V. Luong, A. Arreghini, M. Toledano-Luque, A. Hikavyy, T. Numata, K. De Meyer, G. Van den bosch, J. van Houdt
Epitaxially grown Si and Si0.6Ge0.4 are integrated as replacement of poly-Si channel in vertical cylindrical transistors for vertical NAND memory application, in order to investigate the impact of the grain boundaries on current conduction. Epi-Si outperforms both poly-Si and Epi-SiGe channels, resulting in the best conduction, with large improvement on both sub threshold swing and transconductance (gm). The experimentally observed gm bimodal distribution for epi Si is corroborated and explained through a resistive network model: lower gm conduction occurs when current needs to cross a high resistance boundary, whereas higher gm is obtained when this boundary is not present.
{"title":"Integration and Electrical Evaluation of Epitaxially Grown Si and SiGe Channels for Vertical NAND Memory Applications","authors":"E. Capogreco, R. Degraeve, J. Lisoni, V. Luong, A. Arreghini, M. Toledano-Luque, A. Hikavyy, T. Numata, K. De Meyer, G. Van den bosch, J. van Houdt","doi":"10.1109/IMW.2015.7150291","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150291","url":null,"abstract":"Epitaxially grown Si and Si0.6Ge0.4 are integrated as replacement of poly-Si channel in vertical cylindrical transistors for vertical NAND memory application, in order to investigate the impact of the grain boundaries on current conduction. Epi-Si outperforms both poly-Si and Epi-SiGe channels, resulting in the best conduction, with large improvement on both sub threshold swing and transconductance (gm). The experimentally observed gm bimodal distribution for epi Si is corroborated and explained through a resistive network model: lower gm conduction occurs when current needs to cross a high resistance boundary, whereas higher gm is obtained when this boundary is not present.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115232273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150265
C. Matsui, A. Arakawa, Chao Sun, T. Iwasaki, K. Takeuchi
Solid-state drives (SSDs) are over-taking hard disk drives (HDDs) as high-volume storage in enterprise servers and data centers. However, SSDs write performance is limited due to their inability to overwrite in-place and need for garbage collection. To reduce the garbage collection (GC) overhead, a logical block address (LBA) scrambler has been proposed. However, the LBA scrambler has two issues: (1) SSD performance decreases with a hot and random workload, and (2) the table size of the LBA scrambler may become upto 0.85% of the SSD capacity. In this work, a write order (WO) based GC scheme is proposed to solve the first issue. The number of valid pages in the NAND flash block, the write order and erase count of the block are considered for victim block selection during GC. One of the key advantages of the WO GC is that it does not require a clock inside the SSD, which will not operate if the SSD power is off. Further, to solve the second issue of the large table size, a Sector Bundling scheme is proposed. From the results, SSD performance is improved 3×, and the LBA scrambler table size is reduced 16%.
{"title":"3X Faster Speed Solid-State Drive with a Write Order Based Garbage Collection Scheme","authors":"C. Matsui, A. Arakawa, Chao Sun, T. Iwasaki, K. Takeuchi","doi":"10.1109/IMW.2015.7150265","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150265","url":null,"abstract":"Solid-state drives (SSDs) are over-taking hard disk drives (HDDs) as high-volume storage in enterprise servers and data centers. However, SSDs write performance is limited due to their inability to overwrite in-place and need for garbage collection. To reduce the garbage collection (GC) overhead, a logical block address (LBA) scrambler has been proposed. However, the LBA scrambler has two issues: (1) SSD performance decreases with a hot and random workload, and (2) the table size of the LBA scrambler may become upto 0.85% of the SSD capacity. In this work, a write order (WO) based GC scheme is proposed to solve the first issue. The number of valid pages in the NAND flash block, the write order and erase count of the block are considered for victim block selection during GC. One of the key advantages of the WO GC is that it does not require a clock inside the SSD, which will not operate if the SSD power is off. Further, to solve the second issue of the large table size, a Sector Bundling scheme is proposed. From the results, SSD performance is improved 3×, and the LBA scrambler table size is reduced 16%.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134240787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150292
A. Baiano, M. van Duuren, E. van der Vegt, Bob Schippers, R. Beurze, Daniel Tajari Mofrad, H. van Zwol, Yu Chen, J. Chiang, Han Lokker, K. van Dijk, J. Verbree, Y. Chen, J. Garbe, R. Verhaar, D. Dormans
2-transistor (2T) cell technology used for embedded non-volatile memory (eNVM) has been scaled down to 40nm node. To enable aggressive cell scaling, the array architecture is modified compared to previous generations and the channel length of cell is drastically reduced requiring steep cell junctions, which give rise to new disturb phenomena. This paper describes how to safeguard the drain disturb immunity in 40nm 2T eNVM, while maintaining the intrinsic 2T robustness.
{"title":"Junction Optimization for Embedded 40nm FN/FN Flash Memory","authors":"A. Baiano, M. van Duuren, E. van der Vegt, Bob Schippers, R. Beurze, Daniel Tajari Mofrad, H. van Zwol, Yu Chen, J. Chiang, Han Lokker, K. van Dijk, J. Verbree, Y. Chen, J. Garbe, R. Verhaar, D. Dormans","doi":"10.1109/IMW.2015.7150292","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150292","url":null,"abstract":"2-transistor (2T) cell technology used for embedded non-volatile memory (eNVM) has been scaled down to 40nm node. To enable aggressive cell scaling, the array architecture is modified compared to previous generations and the channel length of cell is drastically reduced requiring steep cell junctions, which give rise to new disturb phenomena. This paper describes how to safeguard the drain disturb immunity in 40nm 2T eNVM, while maintaining the intrinsic 2T robustness.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114621569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150270
Nianduan Lu, Ling Li, P. Sun, Ming Wang, Qi Liu, H. Lv, S. Long, Ming Liu
For the first time, we proposed a physical model to link the macroscopic I-V characteristics with the material microstructure, based on the calculation of activation energy from first-principles calculations. According to the model, a new method for identifying the carrier transport path by using the calculated defect level was developed in RRAM. This developed method may be used to extract the carrier transport path of each operation and quantify the distribution of switching parameters. Based on the transport path, the intrinsic origin of current variation was identified in RRAM. The methods to improve the uniformity of switching parameters are also provided.
{"title":"A Novel Approach to Identify the Carrier Transport Path and Its Correlation to the Current Variation in RRAM","authors":"Nianduan Lu, Ling Li, P. Sun, Ming Wang, Qi Liu, H. Lv, S. Long, Ming Liu","doi":"10.1109/IMW.2015.7150270","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150270","url":null,"abstract":"For the first time, we proposed a physical model to link the macroscopic I-V characteristics with the material microstructure, based on the calculation of activation energy from first-principles calculations. According to the model, a new method for identifying the carrier transport path by using the calculated defect level was developed in RRAM. This developed method may be used to extract the carrier transport path of each operation and quantify the distribution of switching parameters. Based on the transport path, the intrinsic origin of current variation was identified in RRAM. The methods to improve the uniformity of switching parameters are also provided.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"148 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122380130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150304
Sung-Kun Park, Kwang-il Choi, Nam-Yoon Kim, Jung-Hoon Kim, Young-Jun Kwon, Kwangsik Ko, I. Cho, K. Yoo
We report a single-poly embedded nonvolatile memory (eNVM) solution for analog trimming and code storage applications using a 0.13-μm BCDMOS process. Each cell has its own merits and demerits, depending on structure and operation methods. For analog trimming purposes, a conventional n-well coupling Fowler-Nordheim tunneling cell with a large unit cell size of 88 μm2 is used. On the other hand, a select gate lateral coupling (SGLC) cell for code storage purposes has a much smaller unit cell size of 2.82 μm2, which is comparable to the size of SRAM. The SGLC cell is fabricated using a combination of only 1.5-V and 5-V transistor-related processes for channel hot electron injection programming. The SGLC cell exhibits a high programming speed of 100 μs and is over-erase-free, which is suitable for a NOR array structure. In addition, both cells also had a retention lifetime of more than 10 years. Thus, these cells can be fabricated to match the requirements of various eNVM applications.
{"title":"Single-Poly Embedded NVM Solution for Analog Trimming and Code Storage Applications","authors":"Sung-Kun Park, Kwang-il Choi, Nam-Yoon Kim, Jung-Hoon Kim, Young-Jun Kwon, Kwangsik Ko, I. Cho, K. Yoo","doi":"10.1109/IMW.2015.7150304","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150304","url":null,"abstract":"We report a single-poly embedded nonvolatile memory (eNVM) solution for analog trimming and code storage applications using a 0.13-μm BCDMOS process. Each cell has its own merits and demerits, depending on structure and operation methods. For analog trimming purposes, a conventional n-well coupling Fowler-Nordheim tunneling cell with a large unit cell size of 88 μm2 is used. On the other hand, a select gate lateral coupling (SGLC) cell for code storage purposes has a much smaller unit cell size of 2.82 μm2, which is comparable to the size of SRAM. The SGLC cell is fabricated using a combination of only 1.5-V and 5-V transistor-related processes for channel hot electron injection programming. The SGLC cell exhibits a high programming speed of 100 μs and is over-erase-free, which is suitable for a NOR array structure. In addition, both cells also had a retention lifetime of more than 10 years. Thus, these cells can be fabricated to match the requirements of various eNVM applications.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127640009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150264
H. Koike, S. Miura, H. Honjo, Tosinari Watanabe, Hideo Sato, S. Sato, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, M. Muraguchi, M. Niwa, Kenchi Ito, S. Ikeda, H. Ohno, T. Endoh
A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array design with a high-signal-margin reference generator circuit was developed to create high-density 1T1MTJ STT-MRAMs. To realize an appropriate STT-MRAM design, fluctuations in the memory cell characteristics were first measured using a 1-kbit STT-MRAM test chip. Based on these measurements, a reference generator and an STT-MRAM cell array architecture were proposed. This cell array was evaluated in terms of the signal margin for read operation and its tolerance to device variation by means of Monte-Carlo SPICE circuit simulations. The proposed design enables a 50% improvement in the signal margin compared with the conventional cell array circuit.
{"title":"1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator for Improving Device Variation Tolerance","authors":"H. Koike, S. Miura, H. Honjo, Tosinari Watanabe, Hideo Sato, S. Sato, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, M. Muraguchi, M. Niwa, Kenchi Ito, S. Ikeda, H. Ohno, T. Endoh","doi":"10.1109/IMW.2015.7150264","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150264","url":null,"abstract":"A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array design with a high-signal-margin reference generator circuit was developed to create high-density 1T1MTJ STT-MRAMs. To realize an appropriate STT-MRAM design, fluctuations in the memory cell characteristics were first measured using a 1-kbit STT-MRAM test chip. Based on these measurements, a reference generator and an STT-MRAM cell array architecture were proposed. This cell array was evaluated in terms of the signal margin for read operation and its tolerance to device variation by means of Monte-Carlo SPICE circuit simulations. The proposed design enables a 50% improvement in the signal margin compared with the conventional cell array circuit.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126874782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150267
N. Do, L. Tee, S. Hariharan, S. Lemke, M. Tadayoni, W. Yang, M. Wu, JinHo Kim, Yueh-Hsin Chen, C. Su, V. Tiwari, Stephen Zhou, R. Qian, I. Yue
In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually be scaled to 40 nm and smaller lithographically nodes, without compromising performance and reliability.
{"title":"A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability","authors":"N. Do, L. Tee, S. Hariharan, S. Lemke, M. Tadayoni, W. Yang, M. Wu, JinHo Kim, Yueh-Hsin Chen, C. Su, V. Tiwari, Stephen Zhou, R. Qian, I. Yue","doi":"10.1109/IMW.2015.7150267","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150267","url":null,"abstract":"In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually be scaled to 40 nm and smaller lithographically nodes, without compromising performance and reliability.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125216277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150307
Sung-Kye Park
Memory manufactures are facing the challenges of technology scaling beyond 1xnm node DRAM and NAND flash memory. Even though we are managing to overcome patterning issue, we are still fighting against cost reduction and electrical limitation. In this paper, the scaling limitations and challenges of both DRAM and NAND are reviewed, and the future prospects with promising solutions are also addressed for high density DRAM and 3D NAND flash memory.
{"title":"Technology Scaling Challenge and Future Prospects of DRAM and NAND Flash Memory","authors":"Sung-Kye Park","doi":"10.1109/IMW.2015.7150307","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150307","url":null,"abstract":"Memory manufactures are facing the challenges of technology scaling beyond 1xnm node DRAM and NAND flash memory. Even though we are managing to overcome patterning issue, we are still fighting against cost reduction and electrical limitation. In this paper, the scaling limitations and challenges of both DRAM and NAND are reviewed, and the future prospects with promising solutions are also addressed for high density DRAM and 3D NAND flash memory.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127604335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150274
Kosuke Suzuki, S. Swanson
We present a survey of non-volatile memory technology papers published between 2000 and 2014 in leading journals and conference proceedings in the area of integrated circuit design and semiconductor devices. We present a summary of the data provided in these papers and use that data to model basic aspects of their performance at an architectural level. The full data set and complete bibliography will be published online.
{"title":"A Survey of Trends in Non-Volatile Memory Technologies: 2000-2014","authors":"Kosuke Suzuki, S. Swanson","doi":"10.1109/IMW.2015.7150274","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150274","url":null,"abstract":"We present a survey of non-volatile memory technology papers published between 2000 and 2014 in leading journals and conference proceedings in the area of integrated circuit design and semiconductor devices. We present a summary of the data provided in these papers and use that data to model basic aspects of their performance at an architectural level. The full data set and complete bibliography will be published online.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132714106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-17DOI: 10.1109/IMW.2015.7150286
B. Desalvo, E. Vianello, D. Garbin, O. Bichler, L. Perniola
In this work, we will focus on the role that new nonvolatile resistive memory technologies (as OxRAM and CBRAM) can play in emerging fields of application, such as neuromorphic circuits, to save energy and increase performance. We will present large-scale energy efficient neuromorphic systems based on ReRAM as stochastic-binary synapses. Prototype applications such as complex visual- and auditory-pattern extraction will be discussed using feedforward spiking neural networks. A parallel will be drawn between these systems and human memory, as recent discoveries on the human brain and cognitive processes may bring benefits and open new perspectives for intelligent data processing.
{"title":"From Memory in our Brain to Emerging Resistive Memories in Neuromorphic Systems","authors":"B. Desalvo, E. Vianello, D. Garbin, O. Bichler, L. Perniola","doi":"10.1109/IMW.2015.7150286","DOIUrl":"https://doi.org/10.1109/IMW.2015.7150286","url":null,"abstract":"In this work, we will focus on the role that new nonvolatile resistive memory technologies (as OxRAM and CBRAM) can play in emerging fields of application, such as neuromorphic circuits, to save energy and increase performance. We will present large-scale energy efficient neuromorphic systems based on ReRAM as stochastic-binary synapses. Prototype applications such as complex visual- and auditory-pattern extraction will be discussed using feedforward spiking neural networks. A parallel will be drawn between these systems and human memory, as recent discoveries on the human brain and cognitive processes may bring benefits and open new perspectives for intelligent data processing.","PeriodicalId":107437,"journal":{"name":"2015 IEEE International Memory Workshop (IMW)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133282632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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