V. Krishnaswamy, Jinuk Luke Shin, Sebastian Turullols, J. Hart, G. Konstadinidis, Dawei Huang
{"title":"A 28nm 3.6GHz 128 thread SPARC T5 processor and system applications","authors":"V. Krishnaswamy, Jinuk Luke Shin, Sebastian Turullols, J. Hart, G. Konstadinidis, Dawei Huang","doi":"10.1109/ASSCC.2013.6690971","DOIUrl":null,"url":null,"abstract":"The SPARC T5 processor implements 16 8-threaded SPARC S3 cores, an 8-MB 16-way set-associative L3 cache, 8 BL8 DDR3-1066 schedulers, and integrated PCIe Gen-3. The processor doubles the performance of the previous generation SPARC T4 CPU and expands support for up to 8 socket systems in a single hop glueless fashion. It is implemented in the TSMC 28nm process using 1.5 billion transistors and a 13 layer metal stack. The chip has a maximum operating frequency of 3.6 GHz.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6690971","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The SPARC T5 processor implements 16 8-threaded SPARC S3 cores, an 8-MB 16-way set-associative L3 cache, 8 BL8 DDR3-1066 schedulers, and integrated PCIe Gen-3. The processor doubles the performance of the previous generation SPARC T4 CPU and expands support for up to 8 socket systems in a single hop glueless fashion. It is implemented in the TSMC 28nm process using 1.5 billion transistors and a 13 layer metal stack. The chip has a maximum operating frequency of 3.6 GHz.
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