N. Miura, Y. Domae, T. Sakata, M. Watanabe, T. Okamura, T. Chiba, K. Fukuda, J. Ida
{"title":"Undoped thin film FD-SOI CMOS with source/drain-to-gate non-overlapped structure for ultra low leak applications","authors":"N. Miura, Y. Domae, T. Sakata, M. Watanabe, T. Okamura, T. Chiba, K. Fukuda, J. Ida","doi":"10.1109/SOI.2005.1563579","DOIUrl":null,"url":null,"abstract":"In this paper, we present an undoped thin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS with source/drain-to-gate non-overlapped structure for ultra low leak (ULL) transistor. The fabricated device achieved a cutoff frequency f/sub T/ of 65GHz with I/sub off/< 0.1pA//spl mu/m (GIDL-free). The proposed inverted-gate implantation/planar-type SOI is practical and low-cost solution for coin-battery applications.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2005.1563579","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
In this paper, we present an undoped thin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS with source/drain-to-gate non-overlapped structure for ultra low leak (ULL) transistor. The fabricated device achieved a cutoff frequency f/sub T/ of 65GHz with I/sub off/< 0.1pA//spl mu/m (GIDL-free). The proposed inverted-gate implantation/planar-type SOI is practical and low-cost solution for coin-battery applications.