Unified MOSFET scaling theory using variational method

Abstract

Using the variational method, the two dimensional Poisson Equation is solved in the MOSFET device region including the gate oxide region, depletion region and buried oxide region (for SOI device). An analytical expression for the potential distribution together with a new natural gate length scale for MOSFET is derived. The 2-D effects in front gate dielectric, back gate dielectric and silicon film can all be taken into account in this derivation. The validity of electrical equivalent oxide thickness approximation is also investigated using this model. Comparison of the short channel effect for uniform channel doping bulk MOSFET, intrinsic channel doping bulk MOSFET, SOI MOSFET and double gated MOSFET is conducted using our model. The results are verified by 2D numerical simulation using the 2D device simulator MEDICI.