{"title":"A filterless digital audio class-D amplifier based on grow-left double-edge pulse width modulation","authors":"Xiaolei Chen, Haipeng Qu, Zeqi Yu, Chunyang Zhang, Enguang Zhang","doi":"10.1109/ICAM.2017.8242175","DOIUrl":null,"url":null,"abstract":"A filterless digital audio class-D amplifier (CDA) based on grow-Left double-edge (GLDE) pulse width modulation (PWM) is proposed in this paper. It consists of a high performance fully-digital uniform-sampling PWM (UPWM) modulator and a bridge-tied-load (BTL) power stage. Due to adopt the ternary PWM modulation scheme, the filterless solution without LC low-pass filter becomes possible. Finally, the error of the BTL power stage is properly corrected to make this amplifier system have a high power supply rejection ratio (PSRR) and a high signal to noise ratio (SNR). The whole design is implemented on Matlab and Cadence platform, combining with 5V 0.35-μm CMOS process technology.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAM.2017.8242175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A filterless digital audio class-D amplifier (CDA) based on grow-Left double-edge (GLDE) pulse width modulation (PWM) is proposed in this paper. It consists of a high performance fully-digital uniform-sampling PWM (UPWM) modulator and a bridge-tied-load (BTL) power stage. Due to adopt the ternary PWM modulation scheme, the filterless solution without LC low-pass filter becomes possible. Finally, the error of the BTL power stage is properly corrected to make this amplifier system have a high power supply rejection ratio (PSRR) and a high signal to noise ratio (SNR). The whole design is implemented on Matlab and Cadence platform, combining with 5V 0.35-μm CMOS process technology.
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