Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242181
Zhao Lv, Shuming Chen, Yaohua Wang
Functional verification is one of the key problems hindering successful design of large and complex hardware. As the base of functional verification, summary and decomposition of function points are leak-prone due to lack of standard language to abstract function points from specification. In this paper, we propose a function abstraction language, FAL, which is used for describing function points from specification. Besides, we develop a corresponding compiler, which can automatically generate the corresponding verification platform given any FAL description. The auto-generated verification platform can generate efficient test sequences, check the properties of function points and record the simulation information and coverage report. The experimental results show that compared with the random test generation, the procedure convergence of our proposal is much faster. In addition, compared with the manual work, the proposed automatic verification framework can lead to 46.6% reduction of time on average in building verification platform.
{"title":"FAL: A function abstraction language for verification automation","authors":"Zhao Lv, Shuming Chen, Yaohua Wang","doi":"10.1109/ICAM.2017.8242181","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242181","url":null,"abstract":"Functional verification is one of the key problems hindering successful design of large and complex hardware. As the base of functional verification, summary and decomposition of function points are leak-prone due to lack of standard language to abstract function points from specification. In this paper, we propose a function abstraction language, FAL, which is used for describing function points from specification. Besides, we develop a corresponding compiler, which can automatically generate the corresponding verification platform given any FAL description. The auto-generated verification platform can generate efficient test sequences, check the properties of function points and record the simulation information and coverage report. The experimental results show that compared with the random test generation, the procedure convergence of our proposal is much faster. In addition, compared with the manual work, the proposed automatic verification framework can lead to 46.6% reduction of time on average in building verification platform.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120991740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An optimization design of an Under Voltage Lockout (UVLO) circuit in a bipolar CMOS DMOS (BCD) process is presented in this paper. Compared with the traditional structure, the proposed circuit effectively reduces the hysteresis voltage drift with temperature by introducing the high-order temperature compensation function to the band-gap reference. Thus, the reliability of the UVLO circuit is improved. The designed UVLO circuit has an input high threshold voltage of 8.2 V, low threshold voltage of 5.6 V and a hysteresis range of 2.6 V when T = 25C. The maximum deviation is 0.3V within −30 ∼ 140C. In a standard BCD process, the designed circuit is simulated by using Spectre in Cadence. The feasibility and correctness of the designed UVLO circuit is proven by the simulation results.
{"title":"Optimization design of under voltage lockout circuit in power management chips based on standard BCD process","authors":"Shulin Liu, Qianqian Wang, Chaoying Wang, Zhi Huang","doi":"10.1109/ICAM.2017.8242143","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242143","url":null,"abstract":"An optimization design of an Under Voltage Lockout (UVLO) circuit in a bipolar CMOS DMOS (BCD) process is presented in this paper. Compared with the traditional structure, the proposed circuit effectively reduces the hysteresis voltage drift with temperature by introducing the high-order temperature compensation function to the band-gap reference. Thus, the reliability of the UVLO circuit is improved. The designed UVLO circuit has an input high threshold voltage of 8.2 V, low threshold voltage of 5.6 V and a hysteresis range of 2.6 V when T = 25C. The maximum deviation is 0.3V within −30 ∼ 140C. In a standard BCD process, the designed circuit is simulated by using Spectre in Cadence. The feasibility and correctness of the designed UVLO circuit is proven by the simulation results.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126858654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242148
Chuansheng Zhang, B. Wang, Yulu Chen, Liwei Hou, M. Pan, Xiaodong Wang
We have developed a GaAs-based Blocked-Impurity-Band (BIB) Detector for the application of Terahertz (THz) security check and astronomical observation. In this work, we have fabricated GaAs:Si and GaAs:Te BIB detectors and analyzed their spectral response characteristics at 3.5K The experimental results of GaAs:Si BIB device demonstrate that the spectral response increases when the bias rises from 0.2 to 2.8V, and the peak wavelength is around 190 μm. The doping elements can form several discrete energy levels in the absorbing layer of GaAs:Si and GaAs:Te BIB detectors, which induce multi-peaks in the spectra. Our results show the potential of GaAs-based BIB detectors as novel, broad-spectrum, and high-performance THz detectors.
{"title":"Study on the spectral response characteristics of GaAs-based blocked-impurity-band detectors","authors":"Chuansheng Zhang, B. Wang, Yulu Chen, Liwei Hou, M. Pan, Xiaodong Wang","doi":"10.1109/ICAM.2017.8242148","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242148","url":null,"abstract":"We have developed a GaAs-based Blocked-Impurity-Band (BIB) Detector for the application of Terahertz (THz) security check and astronomical observation. In this work, we have fabricated GaAs:Si and GaAs:Te BIB detectors and analyzed their spectral response characteristics at 3.5K The experimental results of GaAs:Si BIB device demonstrate that the spectral response increases when the bias rises from 0.2 to 2.8V, and the peak wavelength is around 190 μm. The doping elements can form several discrete energy levels in the absorbing layer of GaAs:Si and GaAs:Te BIB detectors, which induce multi-peaks in the spectra. Our results show the potential of GaAs-based BIB detectors as novel, broad-spectrum, and high-performance THz detectors.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122995904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242134
Chen Sixiang, L. Xiuqin, Liu Yijun, Zeng Qinghui, W. Yunfei, Huang Jing
Lightning is an important factor in the biosafety of the surrounding area of the tower, and its core lies in the dispersed current damage. Lightning current flows into the earth, resulting in the imbalance of current, the unbalance of current leads to the unbalance of the voltage around the tower. Aiming at the problem of lack of soil dispersed current test and safety assessment, the experiment of the unbalance of lightning dispersed current is designed, the dispersed current unbalance under the standard lightning impulse is determined. On this basis, the soil dispersed current measurement and evaluation device of lightning tower was developed. The software of the host computer was written by LabVIEW and applied to the test of soil dispersed current. Finally, the practicability of the measurement and evaluation device was verified by experiments.
{"title":"Study on unbalanced measurement technology of lighting dispersed current in the peripheral area of transmission line","authors":"Chen Sixiang, L. Xiuqin, Liu Yijun, Zeng Qinghui, W. Yunfei, Huang Jing","doi":"10.1109/ICAM.2017.8242134","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242134","url":null,"abstract":"Lightning is an important factor in the biosafety of the surrounding area of the tower, and its core lies in the dispersed current damage. Lightning current flows into the earth, resulting in the imbalance of current, the unbalance of current leads to the unbalance of the voltage around the tower. Aiming at the problem of lack of soil dispersed current test and safety assessment, the experiment of the unbalance of lightning dispersed current is designed, the dispersed current unbalance under the standard lightning impulse is determined. On this basis, the soil dispersed current measurement and evaluation device of lightning tower was developed. The software of the host computer was written by LabVIEW and applied to the test of soil dispersed current. Finally, the practicability of the measurement and evaluation device was verified by experiments.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128264636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242171
Xiuyun Zhou, Yaqiu Chen, Xiaochuan Lu
In order to solve defect detection problem of small-size solder ball in the high density chip, the method based on the pulsed eddy current thermal imaging technology (ECPT) was put forward to study the solder ball defects. With establishing 3D induction heating finite element model, the defects such as cracks, voids can be distinguished by comparing the different temperature field. Furthermore, the experiments with solder balls of different defects and various crack size are carried out. Both experiment result and simulation study verify the reliability and convenience of ECPT method.
{"title":"Study on detection method of small-size solder ball defects","authors":"Xiuyun Zhou, Yaqiu Chen, Xiaochuan Lu","doi":"10.1109/ICAM.2017.8242171","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242171","url":null,"abstract":"In order to solve defect detection problem of small-size solder ball in the high density chip, the method based on the pulsed eddy current thermal imaging technology (ECPT) was put forward to study the solder ball defects. With establishing 3D induction heating finite element model, the defects such as cracks, voids can be distinguished by comparing the different temperature field. Furthermore, the experiments with solder balls of different defects and various crack size are carried out. Both experiment result and simulation study verify the reliability and convenience of ECPT method.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129442056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242159
W. Shuang, W. Xiaodong, Zhao Ting, Du Xiaomeng, Zuo Jia
Electrochemical reaction is the reason of smart meters failure under maritime climate coastal southeastern China. In order to ensure the smart meter runs reliable and stable under this kind of environment, the paper researches three anti-technology based on an analysis of the electrochemical reaction principle, combined with the specific circumstances of meter. In this paper, it analysis the core of three anti-technology theoretically firstly, and then designs experiments and analyses results of the test which verified three anti-technology can improve stability and reliability of smart meters. At the end of the paper, it gives practical suggestion of three anti-technology in smart meters.
{"title":"Study of multi-proofing's technology on smart meter in the area of maritime climate","authors":"W. Shuang, W. Xiaodong, Zhao Ting, Du Xiaomeng, Zuo Jia","doi":"10.1109/ICAM.2017.8242159","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242159","url":null,"abstract":"Electrochemical reaction is the reason of smart meters failure under maritime climate coastal southeastern China. In order to ensure the smart meter runs reliable and stable under this kind of environment, the paper researches three anti-technology based on an analysis of the electrochemical reaction principle, combined with the specific circumstances of meter. In this paper, it analysis the core of three anti-technology theoretically firstly, and then designs experiments and analyses results of the test which verified three anti-technology can improve stability and reliability of smart meters. At the end of the paper, it gives practical suggestion of three anti-technology in smart meters.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129122831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242126
W. Lai, S. Jang, Chunjie Wang
This letter proposes a new concurrent CMOS voltage-controlled oscillator (VCO). The oscillator consists of two sub-VCO operates at 4GHz and 6GHz respectively. The two sub-VCOs are coupled by a pair of MIM capacitors. The proposed oscillator has been implemented with the TSMC 0.18μm BiCMOS technology. By controlling the supply voltages, the VCO has three different operational modes, capable of generating a single frequency in either the 4- or 6-GHz band as well as two frequencies in the 4- and 6-GHz bands simultaneously. In the concurrent mode, the VCO can generate differential signals at 4GHz, 6GHz and their harmonics and other cross-modulation products. The measured phase noise at 1-MHz offset frequency is −111.99 and −121.75 dBc/Hz when the oscillator oscillates at a single frequency of 6.24 or 4.03 GHz, respectively. The phase noise is −113.41 and −108.94 dBc/Hz, respectively, when the oscillator oscillates at 3.97 and 6.64 GHz simultaneously. The die area of the concurrent oscillator is 1.178×0.583 mm2.
{"title":"Concurrent VCO using capacitive coupled oscillators","authors":"W. Lai, S. Jang, Chunjie Wang","doi":"10.1109/ICAM.2017.8242126","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242126","url":null,"abstract":"This letter proposes a new concurrent CMOS voltage-controlled oscillator (VCO). The oscillator consists of two sub-VCO operates at 4GHz and 6GHz respectively. The two sub-VCOs are coupled by a pair of MIM capacitors. The proposed oscillator has been implemented with the TSMC 0.18μm BiCMOS technology. By controlling the supply voltages, the VCO has three different operational modes, capable of generating a single frequency in either the 4- or 6-GHz band as well as two frequencies in the 4- and 6-GHz bands simultaneously. In the concurrent mode, the VCO can generate differential signals at 4GHz, 6GHz and their harmonics and other cross-modulation products. The measured phase noise at 1-MHz offset frequency is −111.99 and −121.75 dBc/Hz when the oscillator oscillates at a single frequency of 6.24 or 4.03 GHz, respectively. The phase noise is −113.41 and −108.94 dBc/Hz, respectively, when the oscillator oscillates at 3.97 and 6.64 GHz simultaneously. The die area of the concurrent oscillator is 1.178×0.583 mm2.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125474640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242139
Yang Ping, Li Da Gang, Li Yong Kai
In whole system, the user usually only offers a voltage with noise as input logic voltage to digital receiver, to guarantee the right logic control, it requires that the IC chip must have a stable inversion level with logic high and logic low input voltage. For COMS process, in traditional design scheme, it usually uses a normal digital inverter as input-unit schematic, and changes the width or length in PMOS and NMOS to change the inversion level of digital receiver. But in this way, the inversion level is depends on process, and it also will be changed with temperature or power noise, for whole system, it is very bad. So this paper introduces three kinds of stable inversion level schematic. They all use the degenerative feedback to stable inversion level. It completely depends on schematic of input-port in receiver, and is also very stable with temperature and power noise.
{"title":"The design of stable logic input inversion level on IC chip","authors":"Yang Ping, Li Da Gang, Li Yong Kai","doi":"10.1109/ICAM.2017.8242139","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242139","url":null,"abstract":"In whole system, the user usually only offers a voltage with noise as input logic voltage to digital receiver, to guarantee the right logic control, it requires that the IC chip must have a stable inversion level with logic high and logic low input voltage. For COMS process, in traditional design scheme, it usually uses a normal digital inverter as input-unit schematic, and changes the width or length in PMOS and NMOS to change the inversion level of digital receiver. But in this way, the inversion level is depends on process, and it also will be changed with temperature or power noise, for whole system, it is very bad. So this paper introduces three kinds of stable inversion level schematic. They all use the degenerative feedback to stable inversion level. It completely depends on schematic of input-port in receiver, and is also very stable with temperature and power noise.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127618639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242183
F. Yuan
This paper provides a comprehensive treatment of the design techniques of all-digital time integrators for time-mode signal processing (TMSP). A detailed examination of the principle, circuit implementation, operation, constraints, and limitations of time adders constructed from switched delay units (SDUs), dual discharge paths (DDP), and unidirectional gated delay lines (UDGDLs) is provided. It is followed with the presentation of three time registers evolved from the studied time adders and a qualitative comparison of their pros and cons. Finally, time integrators developed from the preceding time adders and time registers are studied and their characteristics are compared.
{"title":"Design techniques of all-digital time integrators for time-mode signal processing","authors":"F. Yuan","doi":"10.1109/ICAM.2017.8242183","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242183","url":null,"abstract":"This paper provides a comprehensive treatment of the design techniques of all-digital time integrators for time-mode signal processing (TMSP). A detailed examination of the principle, circuit implementation, operation, constraints, and limitations of time adders constructed from switched delay units (SDUs), dual discharge paths (DDP), and unidirectional gated delay lines (UDGDLs) is provided. It is followed with the presentation of three time registers evolved from the studied time adders and a qualitative comparison of their pros and cons. Finally, time integrators developed from the preceding time adders and time registers are studied and their characteristics are compared.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123908702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ICAM.2017.8242166
Jun Zhao, Xiaohong Peng, Li-gang Hou, Yinan Zhang, Guoqing Sun
A high order curvature-compensated CMOS bandgap voltage reference(BGR) is presented in TSMC 0.35μm CMOS technology with low power low temperature-coefficient(TC) and high power supply rejection ratio(PSRR). The design is used in low dropout regulators which is applied in implanted chips. TC is compensated by adjusting resistor ratio which have different temperature characteristics. A PSRR enhance circuit is inserted in this circuit to maintain a constant gate-source voltage in the current mirror. A TC is 0.192ppm/°C at 3.3V supply and a line regulation is 4.5ppm/V at room temperature. The circuit has a constant voltage of 1.14 V. The circuit performs a PSRR property of 106dB@1kHz and 46dB@1MHz. The circuit consumes a maximum supply current of 12.42μA and start-up time is 2.04μs.
{"title":"A 12.42μA 0.192ppm/°C high PSRR curvature-compensated CMOS bandgap voltage reference","authors":"Jun Zhao, Xiaohong Peng, Li-gang Hou, Yinan Zhang, Guoqing Sun","doi":"10.1109/ICAM.2017.8242166","DOIUrl":"https://doi.org/10.1109/ICAM.2017.8242166","url":null,"abstract":"A high order curvature-compensated CMOS bandgap voltage reference(BGR) is presented in TSMC 0.35μm CMOS technology with low power low temperature-coefficient(TC) and high power supply rejection ratio(PSRR). The design is used in low dropout regulators which is applied in implanted chips. TC is compensated by adjusting resistor ratio which have different temperature characteristics. A PSRR enhance circuit is inserted in this circuit to maintain a constant gate-source voltage in the current mirror. A TC is 0.192ppm/°C at 3.3V supply and a line regulation is 4.5ppm/V at room temperature. The circuit has a constant voltage of 1.14 V. The circuit performs a PSRR property of 106dB@1kHz and 46dB@1MHz. The circuit consumes a maximum supply current of 12.42μA and start-up time is 2.04μs.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124575515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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