A 1.4mW 8b 350MS/s loop-unrolled SAR ADC with background offset calibration in 40nm CMOS

Abstract

A divide-and-conquer approach to address comparator offset mismatch in loop-unrolled SAR ADC is presented. Redundancy and coarse foreground calibration mitigate MSB comparators offset mismatches. A novel background calibration loop matches LSB comparators offsets to a reference comparator. The proposed scheme avoids a dedicated calibration cycle that would slow down conversion. Additionally, it ensures input common mode voltage tracking for each comparator during both calibration and normal operation, without requiring external inputs or special DAC configuration. This enabled the use of a simple bidirectional single-side switching scheme to eliminate switching logic which further boosts speed and reduces switching power. An 8b prototype ADC achieves 45dB SNDR and a Nyquist FOM of 31.3fJ/conv-step at 350MS/s in 40nm CMOS.