Pub Date : 2016-10-18DOI: 10.1109/ESSCIRC.2016.7598261
Shih-En Chen, Kuang-Wei Cheng
A 433 MHz 54 μW wake-up receiver that supports OOK/FSK/PSK demodulation schemes is proposed. Injection-locking and superregenerative reception provide the capabilities of demodulation and linear amplifications with superior sensitivity and high energy efficiency. For a data rate of 200 kbps and a BER <; 0.1%, the proposed receiver achieves sensitivity of - 80/-78/-77 dBm under OOK/FSK/PSK schemes, respectively. Further, incorporating a loop antenna with a reception of an injection-locked oscillator, the receiver features a low-power mode of 11 μW with an energy efficiency of 55 pJ/bit. A prototype receiver is fabricated in a 0.18-μm CMOS process with an active area of 0.45 mm2.
{"title":"A 433 MHz 54 µW OOK/FSK/PSK compatible wake-up receiver with 11 µW low-power mode based on injection-locked oscillator","authors":"Shih-En Chen, Kuang-Wei Cheng","doi":"10.1109/ESSCIRC.2016.7598261","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598261","url":null,"abstract":"A 433 MHz 54 μW wake-up receiver that supports OOK/FSK/PSK demodulation schemes is proposed. Injection-locking and superregenerative reception provide the capabilities of demodulation and linear amplifications with superior sensitivity and high energy efficiency. For a data rate of 200 kbps and a BER <; 0.1%, the proposed receiver achieves sensitivity of - 80/-78/-77 dBm under OOK/FSK/PSK schemes, respectively. Further, incorporating a loop antenna with a reception of an injection-locked oscillator, the receiver features a low-power mode of 11 μW with an energy efficiency of 55 pJ/bit. A prototype receiver is fabricated in a 0.18-μm CMOS process with an active area of 0.45 mm2.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132382732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-18DOI: 10.1109/ESSDERC.2016.7599586
C. Ayala, A. Bazigos, D. Grogg, U. Drechsler, C. Hagleitner
We present the implementation and experimental verification of the first complete digital logic library based on amorphous carbon (a-C)-coated curved-cantilever nanoelectromechanical (NEM) switch technology. Experimental results for sequential gates - latches and edge-triggered D flip-flops (DFF) - and combinational circuits (NAND, AND) are reported for the first time. The capability of the fabricated NEM switch device to store and maintain charge on internal parasitic capacitances during the off-state is confirmed through measurements of dynamic sequential cells. This complete logic library paves the road towards the development of NEM switch-based microprocessors for ultra-low power logic applications.
{"title":"Experimental demonstration of a nanoelectromechanical switch-based logic library including sequential and combinational gates","authors":"C. Ayala, A. Bazigos, D. Grogg, U. Drechsler, C. Hagleitner","doi":"10.1109/ESSDERC.2016.7599586","DOIUrl":"https://doi.org/10.1109/ESSDERC.2016.7599586","url":null,"abstract":"We present the implementation and experimental verification of the first complete digital logic library based on amorphous carbon (a-C)-coated curved-cantilever nanoelectromechanical (NEM) switch technology. Experimental results for sequential gates - latches and edge-triggered D flip-flops (DFF) - and combinational circuits (NAND, AND) are reported for the first time. The capability of the fabricated NEM switch device to store and maintain charge on internal parasitic capacitances during the off-state is confirmed through measurements of dynamic sequential cells. This complete logic library paves the road towards the development of NEM switch-based microprocessors for ultra-low power logic applications.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"21 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120995292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-18DOI: 10.1109/ESSCIRC.2016.7598343
S. Hasegawa, J. Kadomoto, Atsutake Kosuge, T. Kuroda
An inductive coupling technique for wireless interconnection of side-by-side chips within a package is presented. Data is transferred by using changes in magnetic field that occur when the current in coils on the chips is switched off. The circuit layout area and power consumption of transceivers have respectively been reduced to 1/3 and 1/6. A world-leading transmission rate of 1 Tb/s/mm2, which is faster by a factor of 3, has been achieved with a 0.18 μm CMOS test chip.
{"title":"A 1 Tb/s/mm2 inductive-coupling side-by-side chip link","authors":"S. Hasegawa, J. Kadomoto, Atsutake Kosuge, T. Kuroda","doi":"10.1109/ESSCIRC.2016.7598343","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598343","url":null,"abstract":"An inductive coupling technique for wireless interconnection of side-by-side chips within a package is presented. Data is transferred by using changes in magnetic field that occur when the current in coils on the chips is switched off. The circuit layout area and power consumption of transceivers have respectively been reduced to 1/3 and 1/6. A world-leading transmission rate of 1 Tb/s/mm2, which is faster by a factor of 3, has been achieved with a 0.18 μm CMOS test chip.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123213828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-18DOI: 10.1109/ESSCIRC.2016.7598253
T. Asai, Masafumi Mori, T. Itou, Yasuhiro Take, M. Ikebe, T. Kuroda, M. Motomura
1,000 fps motion vector estimation and classification engine for highspeed computational imaging in a 3D stacked imager/processor module is proposed, prototyped, assembled, and also tested. The module features ThruChip interfaces for high fps image transfer, orders of magnitude more area/power efficient motion vector estimation architecture compared to conventional ones, and a cognitive classification scheme employed on motion vector patterns, enabling the classification of moving objects not possible in conventional proposals.
{"title":"Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces","authors":"T. Asai, Masafumi Mori, T. Itou, Yasuhiro Take, M. Ikebe, T. Kuroda, M. Motomura","doi":"10.1109/ESSCIRC.2016.7598253","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598253","url":null,"abstract":"1,000 fps motion vector estimation and classification engine for highspeed computational imaging in a 3D stacked imager/processor module is proposed, prototyped, assembled, and also tested. The module features ThruChip interfaces for high fps image transfer, orders of magnitude more area/power efficient motion vector estimation architecture compared to conventional ones, and a cognitive classification scheme employed on motion vector patterns, enabling the classification of moving objects not possible in conventional proposals.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128577272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-12DOI: 10.1109/ESSCIRC.2016.7598303
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
This paper presents a 5-50 Gb/s quarter-rate transmitter with a 4-tap feed-forward equalization (FFE) based on multiple-multiplexer (MUX). A bandwidth enhanced 4:1 MUX with the capability of eliminating charge-sharing effect is proposed to increase the maximum operating speed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming technique is designed. Implemented in 65 nm CMOS technology, the transmitter occupying an area of 0.6 mm2 achieves a maximum data rate of 50 Gb/s with an energy efficiency of 3.1 pJ/bit.
{"title":"A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS","authors":"Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang","doi":"10.1109/ESSCIRC.2016.7598303","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598303","url":null,"abstract":"This paper presents a 5-50 Gb/s quarter-rate transmitter with a 4-tap feed-forward equalization (FFE) based on multiple-multiplexer (MUX). A bandwidth enhanced 4:1 MUX with the capability of eliminating charge-sharing effect is proposed to increase the maximum operating speed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming technique is designed. Implemented in 65 nm CMOS technology, the transmitter occupying an area of 0.6 mm2 achieves a maximum data rate of 50 Gb/s with an energy efficiency of 3.1 pJ/bit.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133248036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598297
R. Jansen, S. Lindner
The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus minimising any hot carrier injection and dielectric stress degradation. The presented voltage extension technique is scalable to larger and smaller external voltages and suitable for all twin-well technology feature sizes. The technique using the cascade of complementary latches is applied to the realization of a CAN output driver in a digital twin-well double-oxide 180nm technology featuring both 1.8V 180nm and 3.3V 350nm CMOS devices. The CAN driver consists of two bi-state drivers, which are both in high-impedance state during the CAN recessive state and in the high and respectively low state for the CAN dominant state. The realized prototype driver can handle external voltages between -3V and 16V and exhibits a 1.5V differential output swing on a 60Ohm load over the military temperature range compliant to the CAN automotive standard. To the best of our knowledge this is also the first realization of a CAN driver in a low-voltage digital CMOS technology.
{"title":"High-voltage tolerant bi-state self-biasing output driver using cascade complementary latches in twin-well CMOS technology","authors":"R. Jansen, S. Lindner","doi":"10.1109/ESSCIRC.2016.7598297","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598297","url":null,"abstract":"The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus minimising any hot carrier injection and dielectric stress degradation. The presented voltage extension technique is scalable to larger and smaller external voltages and suitable for all twin-well technology feature sizes. The technique using the cascade of complementary latches is applied to the realization of a CAN output driver in a digital twin-well double-oxide 180nm technology featuring both 1.8V 180nm and 3.3V 350nm CMOS devices. The CAN driver consists of two bi-state drivers, which are both in high-impedance state during the CAN recessive state and in the high and respectively low state for the CAN dominant state. The realized prototype driver can handle external voltages between -3V and 16V and exhibits a 1.5V differential output swing on a 60Ohm load over the military temperature range compliant to the CAN automotive standard. To the best of our knowledge this is also the first realization of a CAN driver in a low-voltage digital CMOS technology.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117051164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598274
Loai G. Salem, J. Buckwalter, P. Mercier
This paper presents a DC-RF power inverter that efficiently synthesizes high-voltage RF waveforms directly from a battery voltage using thin-oxide CMOS switches. Instead of stacking transistors or employing large inductive transformation ratios, high output power is generated by switching individual class-D power amplifier (PA) cells in a 2-phase house-of-cards (HoC) topology to provide voltage addition of the cells outputs without exceeding device voltage ratings, effectively resulting in a solid-state RF impedance transformer. High-efficiency at backoff is then achieved by capacitively combining the output of two HoC networks nominally set to generate different amplitudes, enabling voltage-mode Doherty-like backoff without a bulky transmission line. The PA is implemented in 65nm bulk LP CMOS, operates from 4.8V, and provides a battery-to-RF efficiency above 40% at both 23dBm and 6dB backoff at 720MHz.
{"title":"A recursive house-of-cards digital power amplifier employing a λ/4-less Doherty power combiner in 65nm CMOS","authors":"Loai G. Salem, J. Buckwalter, P. Mercier","doi":"10.1109/ESSCIRC.2016.7598274","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598274","url":null,"abstract":"This paper presents a DC-RF power inverter that efficiently synthesizes high-voltage RF waveforms directly from a battery voltage using thin-oxide CMOS switches. Instead of stacking transistors or employing large inductive transformation ratios, high output power is generated by switching individual class-D power amplifier (PA) cells in a 2-phase house-of-cards (HoC) topology to provide voltage addition of the cells outputs without exceeding device voltage ratings, effectively resulting in a solid-state RF impedance transformer. High-efficiency at backoff is then achieved by capacitively combining the output of two HoC networks nominally set to generate different amplitudes, enabling voltage-mode Doherty-like backoff without a bulky transmission line. The PA is implemented in 65nm bulk LP CMOS, operates from 4.8V, and provides a battery-to-RF efficiency above 40% at both 23dBm and 6dB backoff at 720MHz.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116432632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A lower power and area efficient VP9 and multi-standard video decoder chip is first-reported for Android 4K TV. It supports prevalent MPEG-x, VP-x, RMx, WMV-x and H.26x series video standards in a single chip. Three high-throughput techniques, look-ahead re-mapping, early stage pipeline and dynamic-scheduled bus translation, are proposed. They cuts the processing times by 51.2% compared to the state-of-the-art design [4]. Moreover, two area-efficient techniques, hybrid backward probability update and tile-to-raster scan ordering, are designed to reduce the internal memory size by 10%. A mass-production chip is fabricated in a 28nm CMOS technology with an energy efficiency of 0.19nJ/pixel and an area of 2.6mm2. Compared to the dual-core decoder design [4], this work achieves the identical performance (4K@60fps) with single core which cut one-half of chip area.
{"title":"A 2.6mm2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications","authors":"Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Hue-Min Lin, Chun-Chia Chen, Min-Hao Chiu, P. Chao, Ming-Long Wu, Meng-Jye Hu, Sheng-Jen Wang, Che-Hong Chen, Shun-Hsiang Chuang, Hsiu-Yi Lin, Fu-Chun Yeh, C. Kao, Yi-Chang Chen, Chia-Lin Ho, Yen-Chao Huang, Hsiao-En Chen, Chih-Wen Yang, Hsuan-Wen Peng","doi":"10.1109/ESSCIRC.2016.7598254","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598254","url":null,"abstract":"A lower power and area efficient VP9 and multi-standard video decoder chip is first-reported for Android 4K TV. It supports prevalent MPEG-x, VP-x, RMx, WMV-x and H.26x series video standards in a single chip. Three high-throughput techniques, look-ahead re-mapping, early stage pipeline and dynamic-scheduled bus translation, are proposed. They cuts the processing times by 51.2% compared to the state-of-the-art design [4]. Moreover, two area-efficient techniques, hybrid backward probability update and tile-to-raster scan ordering, are designed to reduce the internal memory size by 10%. A mass-production chip is fabricated in a 28nm CMOS technology with an energy efficiency of 0.19nJ/pixel and an area of 2.6mm2. Compared to the dual-core decoder design [4], this work achieves the identical performance (4K@60fps) with single core which cut one-half of chip area.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124958078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598305
Nachiket V. Desai, A. Chandrakasan
A receiver for efficient wireless power delivery at 6.78MHz from smartphones to IoT devices has been designed in 0.18 μm CMOS. The receiver implements a technique to estimate the end-to-end efficiency and achieve maximum efficiency-point tracking (MEPT) across the charge cycle of a Li-ion battery without needing an explicit communication channel with the transmitter. The MEPT technique is tested using two rectifier topologies designed in the same process - the commonly used synchronous full-bridge and a resonant topology with ZVS for high efficiency. Adding MEPT to the full bridge receiver yields an estimated 7.9% savings in transmitter energy in fully charging a Li-ion battery on the receiver, while using the resonant rectifier with MEPT achieves 13.8% total savings in transmitter energy.
{"title":"A ZVS resonant receiver with maximum efficiency tracking for device-to-device wireless charging","authors":"Nachiket V. Desai, A. Chandrakasan","doi":"10.1109/ESSCIRC.2016.7598305","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598305","url":null,"abstract":"A receiver for efficient wireless power delivery at 6.78MHz from smartphones to IoT devices has been designed in 0.18 μm CMOS. The receiver implements a technique to estimate the end-to-end efficiency and achieve maximum efficiency-point tracking (MEPT) across the charge cycle of a Li-ion battery without needing an explicit communication channel with the transmitter. The MEPT technique is tested using two rectifier topologies designed in the same process - the commonly used synchronous full-bridge and a resonant topology with ZVS for high efficiency. Adding MEPT to the full bridge receiver yields an estimated 7.9% savings in transmitter energy in fully charging a Li-ion battery on the receiver, while using the resonant rectifier with MEPT achieves 13.8% total savings in transmitter energy.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124015292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598233
P. Reynaert, M. Tytgat, Wouter Volkaerts, Alexander Standaert, Yang Zhang, Maxime De Wit, Niels Van Thienen
This paper discusses some of the recent advances and challenges that lie ahead for Polymer Microwave Fibers (PMF). PMF is a communication concept that combines mm-wave chips, metal couplers and cheap plastic fibers. It has some unique benefits over copper wireline and optical which can give it a preferred solution for low-cost, low-weight robust high-speed data-communication such as automotive and industrial Ethernet, consumer-oriented connectivity, signal distribution and more.
{"title":"Polymer Microwave Fibers: A blend of RF, copper and optical communication","authors":"P. Reynaert, M. Tytgat, Wouter Volkaerts, Alexander Standaert, Yang Zhang, Maxime De Wit, Niels Van Thienen","doi":"10.1109/ESSCIRC.2016.7598233","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598233","url":null,"abstract":"This paper discusses some of the recent advances and challenges that lie ahead for Polymer Microwave Fibers (PMF). PMF is a communication concept that combines mm-wave chips, metal couplers and cheap plastic fibers. It has some unique benefits over copper wireline and optical which can give it a preferred solution for low-cost, low-weight robust high-speed data-communication such as automotive and industrial Ethernet, consumer-oriented connectivity, signal distribution and more.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127602510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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