Improving performance of robust Self Adaptive Caches by optimizing the switching algorithm

Abstract

This paper provides an analysis of the performance and overhead for the Self Adaptive cache Memories mechanism (SAM). SAM is a graceful degradation method applied to set associative cache memories that uses remapping for some memory locations to obtain an increase in performance by means of a switching table. We also discuss how a major increase in performance of over 75% can be achieved, while the overall area also decreases with more than 35%, because of minimizing the entries in the switching table, by adding switching bits.