Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783112
E. Vatajelu, J. Figueras
One of the main issues in scaled SRAMs is the increase in static power. A common way to reduce the static power consumption of an SRAM array is to decrease its supply voltage when in memory retention mode. Decreasing the supply voltage however has a strong negative effect on the stability of the SRAM cell. This paper statistically analyzes the behavior of the 6T SRAM cell in data retention mode, under process variability. The failure probabilities under various supply voltages are determined for different technology nodes, and the Data Retention Voltage is determined. For the 45nm PTM SRAM cell under random threshold voltage variation, the Data Retention Voltage is found to be 423mV while for the 16nm PTM SRAM, the DRV is 649mV.
{"title":"Statistical analysis of 6T SRAM data retention voltage under process variation","authors":"E. Vatajelu, J. Figueras","doi":"10.1109/DDECS.2011.5783112","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783112","url":null,"abstract":"One of the main issues in scaled SRAMs is the increase in static power. A common way to reduce the static power consumption of an SRAM array is to decrease its supply voltage when in memory retention mode. Decreasing the supply voltage however has a strong negative effect on the stability of the SRAM cell. This paper statistically analyzes the behavior of the 6T SRAM cell in data retention mode, under process variability. The failure probabilities under various supply voltages are determined for different technology nodes, and the Data Retention Voltage is determined. For the 45nm PTM SRAM cell under random threshold voltage variation, the Data Retention Voltage is found to be 423mV while for the 16nm PTM SRAM, the DRV is 649mV.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116947982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783072
Knut Wold, Slobodan V. Petrovic
Understanding the behavior of a true random number generator (TRNG) is important in order to determine the security of such a design. In this paper, an investigation of a TRNG design based on several oscillator rings implemented in a field programmable gate array (FPGA) is performed in order to determine the amount of true randomness or entropy in this design. A model of the TRNG based on the number of hits in the transition regions generating entropy is proposed. This model takes into account the fact that the jitter of an oscillator ring is not constant, but increases or accumulates if the ring is not sampled in a region close to a transition point where the oscillator ring output changes from logic 0 to logic 1 or vice versa. The model of the TRNG is implemented in MatLab and simulations are performed showing the influence of different design parameters and also the influence of properties of the FPGA device on quality of randomness.
{"title":"Behavioral model of TRNG based on oscillator rings implemented in FPGA","authors":"Knut Wold, Slobodan V. Petrovic","doi":"10.1109/DDECS.2011.5783072","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783072","url":null,"abstract":"Understanding the behavior of a true random number generator (TRNG) is important in order to determine the security of such a design. In this paper, an investigation of a TRNG design based on several oscillator rings implemented in a field programmable gate array (FPGA) is performed in order to determine the amount of true randomness or entropy in this design. A model of the TRNG based on the number of hits in the transition regions generating entropy is proposed. This model takes into account the fact that the jitter of an oscillator ring is not constant, but increases or accumulates if the ring is not sampled in a region close to a transition point where the oscillator ring output changes from logic 0 to logic 1 or vice versa. The model of the TRNG is implemented in MatLab and simulations are performed showing the influence of different design parameters and also the influence of properties of the FPGA device on quality of randomness.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"14 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114130863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783086
Mihkel Tagel, P. Ellervee, T. Hollstein, G. Jervan
This paper addresses the communication modelling and synthesis problem for applications implemented on networks-on-chip. Due to the communication complexity of such systems it is difficult to estimate the communication delay. On the other hand, guaranteeing the timing constraints without detailed know-how about the communication is impossible. In this work we propose a communication modelling and synthesis approach for networks-on-chip where communication infrastructure is not able to provide communication interleaving (such as TDMA, virtual channels) or to guarantee communication delays. The idea is, to design a communication synthesis method, which would not be run off-chip as a CAD tool on a workstation, but on-chip and being activated whenever the system-on-chip (SoC) is re-configured.
{"title":"Communication modelling and synthesis for NoC-based systems with real-time constraints","authors":"Mihkel Tagel, P. Ellervee, T. Hollstein, G. Jervan","doi":"10.1109/DDECS.2011.5783086","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783086","url":null,"abstract":"This paper addresses the communication modelling and synthesis problem for applications implemented on networks-on-chip. Due to the communication complexity of such systems it is difficult to estimate the communication delay. On the other hand, guaranteeing the timing constraints without detailed know-how about the communication is impossible. In this work we propose a communication modelling and synthesis approach for networks-on-chip where communication infrastructure is not able to provide communication interleaving (such as TDMA, virtual channels) or to guarantee communication delays. The idea is, to design a communication synthesis method, which would not be run off-chip as a CAD tool on a workstation, but on-chip and being activated whenever the system-on-chip (SoC) is re-configured.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129138404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783120
Ó. Ruano, J. A. Maestro, P. Reviriego
A methodology based on optimization processes and software fault injection is presented to verify and improve TMR protection against SEUs. It allows validating the reliability achieved by the protection, optimizing the solution area cost.
{"title":"Validation and optimization of TMR protections for circuits in radiation environments","authors":"Ó. Ruano, J. A. Maestro, P. Reviriego","doi":"10.1109/DDECS.2011.5783120","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783120","url":null,"abstract":"A methodology based on optimization processes and software fault injection is presented to verify and improve TMR protection against SEUs. It allows validating the reliability achieved by the protection, optimizing the solution area cost.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124614372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783047
W. Wrona, Pawel Duc, L. Barcik, W. Pietrasina
In this paper we present an example of a DISPLAY-CTRL IP component verification in an SCE-MI based emulation platform. The basic parts of this platform are some transactors. Their task is communication between the testbench written in the high level language SystemC (software side) and the IP component, placing in FPGA on an emulation board (hardware side) through an SCE-MI infrastructure. Using the platform to simulate the DISPLAY-CTRL IP component we achieve a performance increase of about 70x over software only event-driven simulation.
{"title":"An example of DISPLAY-CTRL IP Component verification in SCE-MI based emulation platform","authors":"W. Wrona, Pawel Duc, L. Barcik, W. Pietrasina","doi":"10.1109/DDECS.2011.5783047","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783047","url":null,"abstract":"In this paper we present an example of a DISPLAY-CTRL IP component verification in an SCE-MI based emulation platform. The basic parts of this platform are some transactors. Their task is communication between the testbench written in the high level language SystemC (software side) and the IP component, placing in FPGA on an emulation board (hardware side) through an SCE-MI infrastructure. Using the platform to simulate the DISPLAY-CTRL IP component we achieve a performance increase of about 70x over software only event-driven simulation.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129917945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783066
Farid Lahrach, A. Doumar, E. Châtelet
Fault tolerance is an important system metric to increase chip reliability. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume and weight. In this contribution, we propose a technique based on partial dynamic reconfiguration (PDR) to tolerate faults in configurable logic blocks (CLBs) and routing resources (RRs). The fault tolerance is achieved through SRAM cells of configuration frames. Our method do not require preallocated spare CLBs or RRs. The reliability of frames is analyzed and improved.
{"title":"Fault tolerance of SRAM-based FPGA via configuration frames","authors":"Farid Lahrach, A. Doumar, E. Châtelet","doi":"10.1109/DDECS.2011.5783066","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783066","url":null,"abstract":"Fault tolerance is an important system metric to increase chip reliability. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume and weight. In this contribution, we propose a technique based on partial dynamic reconfiguration (PDR) to tolerate faults in configurable logic blocks (CLBs) and routing resources (RRs). The fault tolerance is achieved through SRAM cells of configuration frames. Our method do not require preallocated spare CLBs or RRs. The reliability of frames is analyzed and improved.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126231392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783126
U. Pešović, S. Randjić, Z. Stamenkovic
The paper presents design and implementation of a wireless sensor node suitable for medical applications. As physiological signals are highly redundant, the data compression algorithms (Huffman's coding) are used to save energy and improve the node performance. Design is based on the ARM Cortex M1 processor and implemented in FPGA.
{"title":"A wireless ECG sensor node based on Huffman data encoder","authors":"U. Pešović, S. Randjić, Z. Stamenkovic","doi":"10.1109/DDECS.2011.5783126","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783126","url":null,"abstract":"The paper presents design and implementation of a wireless sensor node suitable for medical applications. As physiological signals are highly redundant, the data compression algorithms (Huffman's coding) are used to save energy and improve the node performance. Design is based on the ARM Cortex M1 processor and implemented in FPGA.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134603326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783071
S. Irobi, Z. Al-Ars, S. Hamdioui, M. Renovell
Parasitic node capacitance and faulty node voltage of a defective node can induce serious parasitic effects on the electrical behavior of SRAMs. This paper evaluates the impact of parasitic memory effect on the detection of single-cell faults in SRAMs. It demonstrates that detection is significantly influenced by parasitic node components; something that is often not accounted for during memory testing. Finally, it shows the impact of parasitic node components on all possible opens in the SRAM memory cell array, using node voltages from GND to VDD.
{"title":"Influence of parasitic memory effect on single-cell faults in SRAMs","authors":"S. Irobi, Z. Al-Ars, S. Hamdioui, M. Renovell","doi":"10.1109/DDECS.2011.5783071","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783071","url":null,"abstract":"Parasitic node capacitance and faulty node voltage of a defective node can induce serious parasitic effects on the electrical behavior of SRAMs. This paper evaluates the impact of parasitic memory effect on the detection of single-cell faults in SRAMs. It demonstrates that detection is significantly influenced by parasitic node components; something that is often not accounted for during memory testing. Finally, it shows the impact of parasitic node components on all possible opens in the SRAM memory cell array, using node voltages from GND to VDD.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131537839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783114
Xiaoxin Fan, S. Reddy, I. Pomeranz
It was recently observed that the methods to generate scan based tests with low switching activity cause about 40% less activity than functional tests. Thus such tests may cause test escapes as they may not adequately stress the circuits under test. In this work we propose a method called Max-Fill to generate high quality partially-functional broadside delay tests. The generated tests are shown to cause switching activity close to the switching activity during functional operation. The method computes a set of reachable states in which states are likely to cause high switching activity. During test generation phase, these states are used as background states to fill the unspecified bits of test cubes. Additionally, the number of test patterns produced is less than that produced by low power test methods. Experimental results for ISCAS-89 circuits are given.
{"title":"Max-Fill: A method to generate high quality delay tests","authors":"Xiaoxin Fan, S. Reddy, I. Pomeranz","doi":"10.1109/DDECS.2011.5783114","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783114","url":null,"abstract":"It was recently observed that the methods to generate scan based tests with low switching activity cause about 40% less activity than functional tests. Thus such tests may cause test escapes as they may not adequately stress the circuits under test. In this work we propose a method called Max-Fill to generate high quality partially-functional broadside delay tests. The generated tests are shown to cause switching activity close to the switching activity during functional operation. The method computes a set of reachable states in which states are likely to cause high switching activity. During test generation phase, these states are used as background states to fill the unspecified bits of test cubes. Additionally, the number of test patterns produced is less than that produced by low power test methods. Experimental results for ISCAS-89 circuits are given.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133427299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-13DOI: 10.1109/DDECS.2011.5783056
Dae Young Lee, D. Wentzloff, J. Hayes
Wafer testing via direct-contact probe cards has long been an effective and relatively low-cost method for testing integrated circuit (IC) chips prior to packaging. However, the physical contact occurring between the wafer and automatic test equipment (ATE) has significant costs due to contact point deformation and the need for abrasive cleaning. In this paper, we investigate a non-contact testing technique that wirelessly couples an IC wafer and ATE, and serves as an alternative to conventional probe-card testing. We derive several analytical models for a capacitive testing channel. Electromagnetic field simulations results are presented that support the proposed channel models. We conclude that capacitance-based wireless testing is feasible for testing ICs in the 1-GHz range.
{"title":"Wireless wafer-level testing of integrated circuits via capacitively-coupled channels","authors":"Dae Young Lee, D. Wentzloff, J. Hayes","doi":"10.1109/DDECS.2011.5783056","DOIUrl":"https://doi.org/10.1109/DDECS.2011.5783056","url":null,"abstract":"Wafer testing via direct-contact probe cards has long been an effective and relatively low-cost method for testing integrated circuit (IC) chips prior to packaging. However, the physical contact occurring between the wafer and automatic test equipment (ATE) has significant costs due to contact point deformation and the need for abrasive cleaning. In this paper, we investigate a non-contact testing technique that wirelessly couples an IC wafer and ATE, and serves as an alternative to conventional probe-card testing. We derive several analytical models for a capacitive testing channel. Electromagnetic field simulations results are presented that support the proposed channel models. We conclude that capacitance-based wireless testing is feasible for testing ICs in the 1-GHz range.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132200224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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