A High-Speed Level Shifter with dVs/dt Noise Immunity Enhancement Structure for 200V Monolithic GaN Power IC

Abstract

Monolithic integration has been demonstrated to be an ideal solution to minimize the parasitics in GaN power IC. Nonetheless, the current commercially GaN process for power IC is far less mature and only n-type HEMTs are available. Therefore, it is difficult for high voltage level shifters to achieve high speed. This work implements a level shifter for GaN IC to achieve both small response time and high $\mathrm{d}V_{\mathrm{S}}/\text{dt}$ noise immunity without complicated signal processing circuits, thus delay and conduction loss will be minimized. The proposed circuit was fabricated in a $1\mu\mathrm{m}$ GaN-on-Silicon process and measured results were performed to verify the characteristics.