A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication

Abstract

In this paper, resonant clocking is applied to a Viterbi decoder for ultra-low-power WLAN communication. Clock skew balancing and excessive cross-over currents are identified as the most relevant issues: H-clock-trees and a new latch circuit are proposed as innovative power-efficient design solutions. The chip has been integrated in a 0.25 μm CMOS process. Supplied at 1.75 V, the 1.35 mm2 core dissipates 50 mW at 54 Mb/s throughput, with about 27% power savings compared to an equivalent circuit with conventional one-phase single-edge-triggered (SET) clocking strategy and a recently published competitor by C.C. Lin, et al (2005). The chip works up to 77 MHz.