A 0.18V charge-pumped DFF with 50.8% energy-delay reduction for near-/sub-threshold circuits

Abstract

This paper presents a 16-transistor charge-pumped DFF featuring a low energy-delay product for near-/sub-threshold applications. The device count of the proposed DFF is minimized by eliminating clock buffer and employing pass gates instead of transmission gates. To reduce the Clock-to-Q delay and improve variation resilience, two charge pumps and an anti-inverse-narrow-width-effect strategy are utilized, improving the performance by 23%. The proposed DFF is fully functional down to 0.18V and shows the energy-delay product of 13.1 pJ·ns at 100% data activity, achieving 51.8% improvement compared to the conventional TGFF. When VDD=0.5V, the energy-delay product is averagely enhanced by 50.8%. Two 256-bit FIFOs are implemented in 180nm CMOS technology using the proposed DFF and TGFF. The FIFO utilizing the charge-pumped DFF exhibits 31.2% total power reduction at subthreshold regime.