Energy-delay tradeoffs in CMOS digital circuits design

Abstract

Summary form only given. Digital circuit design and optimization techniques have, in the past, been developed with objective of achieving the highest performance possible, regardless of power. Thus the maximal achievable speed of digital circuits was determined primarily by the limits of the technology. However, in deep submicron technologies, power is the limiting factor for performance. Techniques have been presented which opportunistically improve power, or degrade performance to reduce power. These approaches do not directly address the true concern of digital designers, which is obtaining the minimal energy for a given performance. However, how to trade the energy for speed and where should be the optimal design point is neither well understood nor well defined. Every design operates in a design space, which is bound by maximally achievable speed and minimal achievable power. The speed of every digital circuit block can be traded for power and vice versa. Logical Effort technique helps determine transistor sizes for speed being an objective function. However, Logical Effort neglects energy issues and fails to provide a guideline when designing with power budget. We extended the Logical Effort beyond its present limitation and developed it into a tool that provides digital circuit designer with sizing guidelines in energy-delay space. This presentation addresses the primary factors impacting optimization of digital circuits, and a framework for the optimal sizing, comparison, and analysis of energy-efficient designs.