Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611178
C. Sundaram, P. Balsara, S. Vemulapalli, P. Vallur, O. Eliezer
Designing multi-GHz high-speed digital design blocks, using corner based digital design methodology pushes the performance limits to the extreme and provides the designers with very limited insight on the yield issues, with respect to process variation vulnerabilities. In this paper, we propose a statistically aware methodology, for designing high speed digital design blocks, which not only takes into account the process variability but also ensures a yield of -99.5% . We have tested the distribution based methodology on simple digital blocks and compared the results to the existing corner based approach. We also performed these runs on a timing-critical design of a time-to-digital converter (TDC) block and representative paths from a high-speed control unit block of a SoC wireless design and verified that these designs met the performance metrics at the sigma points with -99.5% yield.
{"title":"Yield aware design methodology for sub-100-nanometer digital SOC designs","authors":"C. Sundaram, P. Balsara, S. Vemulapalli, P. Vallur, O. Eliezer","doi":"10.1109/DCAS.2005.1611178","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611178","url":null,"abstract":"Designing multi-GHz high-speed digital design blocks, using corner based digital design methodology pushes the performance limits to the extreme and provides the designers with very limited insight on the yield issues, with respect to process variation vulnerabilities. In this paper, we propose a statistically aware methodology, for designing high speed digital design blocks, which not only takes into account the process variability but also ensures a yield of -99.5% . We have tested the distribution based methodology on simple digital blocks and compared the results to the existing corner based approach. We also performed these runs on a timing-critical design of a time-to-digital converter (TDC) block and representative paths from a high-speed control unit block of a SoC wireless design and verified that these designs met the performance metrics at the sigma points with -99.5% yield.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134491807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611168
R. Staszewski, R. Staszewski
We present an interpolative GFSK/GMSK pulse-shape filtering for wireless RF transmitters. The filter is software controlled to work in a multi-standard radio with an arbitrary reference frequency. The key benefit of this method is no requirement to generate a low-jitter baseband symbol clock, which is especially advantageous when the available reference frequency is not an integer multiple of the symbol rate. Instead, a high-jitter clock obtained by simple fractional-N digital division of the reference frequency is successfully used. The presented transmitter is realized without any analog filtering and is part of a single-chip fully-compliant GSM radio fabricated in a digital 90 nm CMOS process.
{"title":"Interpolative pulse-shape filtering for a GSM/Bluetooth transmitter","authors":"R. Staszewski, R. Staszewski","doi":"10.1109/DCAS.2005.1611168","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611168","url":null,"abstract":"We present an interpolative GFSK/GMSK pulse-shape filtering for wireless RF transmitters. The filter is software controlled to work in a multi-standard radio with an arbitrary reference frequency. The key benefit of this method is no requirement to generate a low-jitter baseband symbol clock, which is especially advantageous when the available reference frequency is not an integer multiple of the symbol rate. Instead, a high-jitter clock obtained by simple fractional-N digital division of the reference frequency is successfully used. The presented transmitter is realized without any analog filtering and is part of a single-chip fully-compliant GSM radio fabricated in a digital 90 nm CMOS process.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117189420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611167
A. Marshall, M. Kulkarni, M. Campise, R. Cleavelin, C. Duvvury, H. Gossner, M. Gostkowski, G. Knoblinger, C. Pacha, C. Russ, K. Schruefer, T. Schulz, K. VonArnim, B. Wilks, W. Xiong
With trends toward smaller geometries and improved circuit performance continuing, an option being investigated is multigate FETs on SOI substrates. SOI lends itself to SOC systems due to its inherently lower noise and ease of integration of analog, digital, RF and power circuits. A critical analog circuit requirement is accurate current mirroring. Here characteristics of fully depleted FinFET current mirrors are presented. Silicon FinFET current mirrors and their bulk planar counterparts have similar performance and matching: a vital requirement for analog circuitry on this type of material.
{"title":"FinFET current mirror design and evaluation","authors":"A. Marshall, M. Kulkarni, M. Campise, R. Cleavelin, C. Duvvury, H. Gossner, M. Gostkowski, G. Knoblinger, C. Pacha, C. Russ, K. Schruefer, T. Schulz, K. VonArnim, B. Wilks, W. Xiong","doi":"10.1109/DCAS.2005.1611167","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611167","url":null,"abstract":"With trends toward smaller geometries and improved circuit performance continuing, an option being investigated is multigate FETs on SOI substrates. SOI lends itself to SOC systems due to its inherently lower noise and ease of integration of analog, digital, RF and power circuits. A critical analog circuit requirement is accurate current mirroring. Here characteristics of fully depleted FinFET current mirrors are presented. Silicon FinFET current mirrors and their bulk planar counterparts have similar performance and matching: a vital requirement for analog circuitry on this type of material.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122609758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611164
K. Iniewski
CMOS technology has now been successfully commercialized in numerous applications for wireless products. Highly integrated system on chip (SOC) parts, with both RF transceiver and complex digital functions on the same die, can be readily acquired on the open market. As wireless technology and usage proliferates, the continuing cost pressures will continue to steer designers to use CMOS. One emerging area is wireless ad-hoc sensor networks for medical, sensing, and environment monitoring applications. Such a network allows new nodes to join or drop easily, and often demands ultra-low power consumption in each node, with power targets of less than 1 mW. These low power targets are important because for portable operation, as silicon shrinks in size, a major component in the bill of material is the battery. This talk explores the choices that analog and RF IC designers have to make in these applications. The paper reviews radio architectures, and the tradeoffs one has to consider for low power consumption. The venerable superheterodyne architecture, along with the low-IF and direct conversion architectures, are discussed. The architectural discussion is followed by examination of circuit level implementation issues of key functions inside the RF transceiver is examined, including LNAs, mixers, transmitters, and frequency synthesis. The impact of modulation scheme on choices for certain blocks is shown. Emerging technologies to integrate highly selective RF filters on-chip are explored, including the use of MEMS.
{"title":"Ultra-low power RF circuits for SOCs in sensor networks","authors":"K. Iniewski","doi":"10.1109/DCAS.2005.1611164","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611164","url":null,"abstract":"CMOS technology has now been successfully commercialized in numerous applications for wireless products. Highly integrated system on chip (SOC) parts, with both RF transceiver and complex digital functions on the same die, can be readily acquired on the open market. As wireless technology and usage proliferates, the continuing cost pressures will continue to steer designers to use CMOS. One emerging area is wireless ad-hoc sensor networks for medical, sensing, and environment monitoring applications. Such a network allows new nodes to join or drop easily, and often demands ultra-low power consumption in each node, with power targets of less than 1 mW. These low power targets are important because for portable operation, as silicon shrinks in size, a major component in the bill of material is the battery. This talk explores the choices that analog and RF IC designers have to make in these applications. The paper reviews radio architectures, and the tradeoffs one has to consider for low power consumption. The venerable superheterodyne architecture, along with the low-IF and direct conversion architectures, are discussed. The architectural discussion is followed by examination of circuit level implementation issues of key functions inside the RF transceiver is examined, including LNAs, mixers, transmitters, and frequency synthesis. The impact of modulation scheme on choices for certain blocks is shown. Emerging technologies to integrate highly selective RF filters on-chip are explored, including the use of MEMS.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134487432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611170
Y. Ho, K. Muhammad, Meng-Chang Lee, C. Hung, J. Wallberg, C. Fernando, P. Cruise, R. Staszewski, D. Leipold, K. Maggio
An RF receiver front-end for a GSM/GPRS radio system-on-chip in a 90 nm digital CMOS technology is presented. The circuit consisting of low noise amplifier, transconductance amplifier and switching mixer, offers 32.5 dB dynamic range with digitally-configurable voltage gain of 40 dB down to 7.5 dB. A series of decimation and discrete-time filtering follows the mixer and performs a highly-linear second-order low-pass filtering to reject close-in interferers. The front-end gains can be configured with an automatic-gain-control to select an optimal setting to form a trade-off between noise figure and linearity and to compensate the process and temperature variations. Even under the digital switching activity, noise figure at the 40 dB maximum gain is 1.8 dB and +50 dBm IIP/sub 2/ at the 34 dB gain. The variation of the input matching versus multiple gains is less than 1 dB. The circuit in total occupies 3.1 mm/sup 2/. The LNA, TA and mixer consume less than 15.3 mA at a supply voltage of 1.4 V.
{"title":"A GSM/GPRS receiver front-end with discrete-time filters in a 90 nm digital CMOS","authors":"Y. Ho, K. Muhammad, Meng-Chang Lee, C. Hung, J. Wallberg, C. Fernando, P. Cruise, R. Staszewski, D. Leipold, K. Maggio","doi":"10.1109/DCAS.2005.1611170","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611170","url":null,"abstract":"An RF receiver front-end for a GSM/GPRS radio system-on-chip in a 90 nm digital CMOS technology is presented. The circuit consisting of low noise amplifier, transconductance amplifier and switching mixer, offers 32.5 dB dynamic range with digitally-configurable voltage gain of 40 dB down to 7.5 dB. A series of decimation and discrete-time filtering follows the mixer and performs a highly-linear second-order low-pass filtering to reject close-in interferers. The front-end gains can be configured with an automatic-gain-control to select an optimal setting to form a trade-off between noise figure and linearity and to compensate the process and temperature variations. Even under the digital switching activity, noise figure at the 40 dB maximum gain is 1.8 dB and +50 dBm IIP/sub 2/ at the 34 dB gain. The variation of the input matching versus multiple gains is less than 1 dB. The circuit in total occupies 3.1 mm/sup 2/. The LNA, TA and mixer consume less than 15.3 mA at a supply voltage of 1.4 V.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123979321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611171
Xiaodong Wu, R. Padakanti, Gonggui Xu, E. Bilhan, J. Meiners
An analog video decoder is a complicated SOC (system-on-chip) with both analog and digital circuits on it, while a multichannel video decoder will have several decoders integrated on the same chip. In this paper, we talk about the design of a four-channel video decoder. We address the common issues met in the SOC design, and how we handle them in this design. The paper covers different kinds of blocks: analog, phase-locked loop (PLL), digital data-path, and microprocessor etc.
{"title":"The design of a single-chip multichannel video decoder","authors":"Xiaodong Wu, R. Padakanti, Gonggui Xu, E. Bilhan, J. Meiners","doi":"10.1109/DCAS.2005.1611171","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611171","url":null,"abstract":"An analog video decoder is a complicated SOC (system-on-chip) with both analog and digital circuits on it, while a multichannel video decoder will have several decoders integrated on the same chip. In this paper, we talk about the design of a four-channel video decoder. We address the common issues met in the SOC design, and how we handle them in this design. The paper covers different kinds of blocks: analog, phase-locked loop (PLL), digital data-path, and microprocessor etc.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124961059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611176
V. Ramakrishnan, P. Balsara
This paper describes a wide range, area efficient, high precision pulse generator, which has applications in ultrawideband communications and VLSI testing. The proposed architecture exploits Vernier delay line method, which is a popular technique used for very fine time digitization. In the proposed method, width of the generated pulse is programmable to the nearest multiple of a constant buffer delay and finer incremental pulse width, less than one buffer delay is generated using Vernier delay line. The pulse generator architecture was designed, simulated and validated using SPICE in 0.18 /spl mu/m CMOS technology and achieves a resolution less than 10 ps. The pulse generator can be programmed to generate pulses with a minimum pulse width of 160 ps and an incremental pulse width of 10 ps in CMOS 0.18 /spl mu/m technology.
{"title":"Very high precision Vernier delay line based CMOS pulse generator","authors":"V. Ramakrishnan, P. Balsara","doi":"10.1109/DCAS.2005.1611176","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611176","url":null,"abstract":"This paper describes a wide range, area efficient, high precision pulse generator, which has applications in ultrawideband communications and VLSI testing. The proposed architecture exploits Vernier delay line method, which is a popular technique used for very fine time digitization. In the proposed method, width of the generated pulse is programmable to the nearest multiple of a constant buffer delay and finer incremental pulse width, less than one buffer delay is generated using Vernier delay line. The pulse generator architecture was designed, simulated and validated using SPICE in 0.18 /spl mu/m CMOS technology and achieves a resolution less than 10 ps. The pulse generator can be programmed to generate pulses with a minimum pulse width of 160 ps and an incremental pulse width of 10 ps in CMOS 0.18 /spl mu/m technology.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132603199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611177
Liming Xiu
"Logic Effort" is academic research in the field of circuit optimization. The aim of this research is to achieve the fastest circuit implementation of a logic function by using the least amount of silicon resource. The fruit of this "Logic Effort" research has been utilized by Magma in real world timing closure practice and has resulted in significant success. However, the "gain" concept used by Magma in its practice is not user-friendly and has caused lot of confusions. This paper introduces several new concepts which can function as a bridge between the "Logic Effort" circuit optimization technique and real world timing closure practice.
{"title":"Several new concepts to bridge the \"Logic Effort\" research and SoC timing closure practice","authors":"Liming Xiu","doi":"10.1109/DCAS.2005.1611177","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611177","url":null,"abstract":"\"Logic Effort\" is academic research in the field of circuit optimization. The aim of this research is to achieve the fastest circuit implementation of a logic function by using the least amount of silicon resource. The fruit of this \"Logic Effort\" research has been utilized by Magma in real world timing closure practice and has resulted in significant success. However, the \"gain\" concept used by Magma in its practice is not user-friendly and has caused lot of confusions. This paper introduces several new concepts which can function as a bridge between the \"Logic Effort\" circuit optimization technique and real world timing closure practice.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124942459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611169
S. Kasnavi, S. Kilambi, B. Crowley, K. Iniewski, B. Kaminska
Wireless sensor networks provide the ability to gather and communicate critical environmental, industrial or security information to enable rapid responses to potential problems. The limited embedded battery life time requires ultra low power sensing, processing and communication systems. To achieve this goal, new approaches at the device, circuit, system and network level need to be pursued (Roundy et al., 2003). Adoption of error control codes (ECC) reduces the required transmit power for reliable communication, while increasing the processing energy of the encoding and decoding operations. This paper discusses the above trade off for systems with and without standard ECC, such as convolutional and Reed Solomon codes. The comparison of the required energy per bit, based on several implemented decoders, shows that the adoption of an ECC with simple decoding structures (such as Reed Solomon) is quite energy efficient. This has specially been observed for long distances.
无线传感器网络提供了收集和交流关键环境、工业或安全信息的能力，从而能够对潜在问题做出快速反应。有限的嵌入式电池寿命需要超低功耗的传感、处理和通信系统。为了实现这一目标，需要在设备、电路、系统和网络层面寻求新的方法(Roundy et al.， 2003)。采用错误控制码(error control code, ECC)降低了可靠通信所需的发射功率，同时增加了编解码操作的处理能量。本文讨论了具有和不具有标准ECC的系统的上述权衡，例如卷积码和里德所罗门码。基于几个实现的解码器的每比特所需能量的比较表明，采用具有简单解码结构(如Reed Solomon)的ECC是相当节能的。这是特别在远距离观察到的。
{"title":"Application of error control codes (ECC) in ultra-low power RF transceivers","authors":"S. Kasnavi, S. Kilambi, B. Crowley, K. Iniewski, B. Kaminska","doi":"10.1109/DCAS.2005.1611169","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611169","url":null,"abstract":"Wireless sensor networks provide the ability to gather and communicate critical environmental, industrial or security information to enable rapid responses to potential problems. The limited embedded battery life time requires ultra low power sensing, processing and communication systems. To achieve this goal, new approaches at the device, circuit, system and network level need to be pursued (Roundy et al., 2003). Adoption of error control codes (ECC) reduces the required transmit power for reliable communication, while increasing the processing energy of the encoding and decoding operations. This paper discusses the above trade off for systems with and without standard ECC, such as convolutional and Reed Solomon codes. The comparison of the required energy per bit, based on several implemented decoders, shows that the adoption of an ECC with simple decoding structures (such as Reed Solomon) is quite energy efficient. This has specially been observed for long distances.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130821564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611166
V. Oklobdzija
Summary form only given. Digital circuit design and optimization techniques have, in the past, been developed with objective of achieving the highest performance possible, regardless of power. Thus the maximal achievable speed of digital circuits was determined primarily by the limits of the technology. However, in deep submicron technologies, power is the limiting factor for performance. Techniques have been presented which opportunistically improve power, or degrade performance to reduce power. These approaches do not directly address the true concern of digital designers, which is obtaining the minimal energy for a given performance. However, how to trade the energy for speed and where should be the optimal design point is neither well understood nor well defined. Every design operates in a design space, which is bound by maximally achievable speed and minimal achievable power. The speed of every digital circuit block can be traded for power and vice versa. Logical Effort technique helps determine transistor sizes for speed being an objective function. However, Logical Effort neglects energy issues and fails to provide a guideline when designing with power budget. We extended the Logical Effort beyond its present limitation and developed it into a tool that provides digital circuit designer with sizing guidelines in energy-delay space. This presentation addresses the primary factors impacting optimization of digital circuits, and a framework for the optimal sizing, comparison, and analysis of energy-efficient designs.
{"title":"Energy-delay tradeoffs in CMOS digital circuits design","authors":"V. Oklobdzija","doi":"10.1109/DCAS.2005.1611166","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611166","url":null,"abstract":"Summary form only given. Digital circuit design and optimization techniques have, in the past, been developed with objective of achieving the highest performance possible, regardless of power. Thus the maximal achievable speed of digital circuits was determined primarily by the limits of the technology. However, in deep submicron technologies, power is the limiting factor for performance. Techniques have been presented which opportunistically improve power, or degrade performance to reduce power. These approaches do not directly address the true concern of digital designers, which is obtaining the minimal energy for a given performance. However, how to trade the energy for speed and where should be the optimal design point is neither well understood nor well defined. Every design operates in a design space, which is bound by maximally achievable speed and minimal achievable power. The speed of every digital circuit block can be traded for power and vice versa. Logical Effort technique helps determine transistor sizes for speed being an objective function. However, Logical Effort neglects energy issues and fails to provide a guideline when designing with power budget. We extended the Logical Effort beyond its present limitation and developed it into a tool that provides digital circuit designer with sizing guidelines in energy-delay space. This presentation addresses the primary factors impacting optimization of digital circuits, and a framework for the optimal sizing, comparison, and analysis of energy-efficient designs.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117288275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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