{"title":"Reliability analysis of next generation wafer level chip scale","authors":"Qiuxiao Qian, Y. Liu","doi":"10.1109/EUROSIME.2013.6529987","DOIUrl":null,"url":null,"abstract":"In this paper, the reliability performance of next generation WLCSP is studied through modeling. Intensive study is carried out from single bump design to package dimension design and the application design in PCB board. Polyimide, solder joint array layout with different width and length ratio and the PCB board via layout are simulated to improve the reliability performance. The models with different polyimide layouts and different material are studied in both thermal cycling and drop test. Then, the impact of different bump array width and length ratio on the next generation of the WLCSP is studied for the reliability performance. Finally, the impact of different PCB board via design and layout on the reliability performance of next generation WLCSP is analyzed in thermal cycling test. Different through board vias and blind vias array in PCB board are studied.","PeriodicalId":270532,"journal":{"name":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUROSIME.2013.6529987","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this paper, the reliability performance of next generation WLCSP is studied through modeling. Intensive study is carried out from single bump design to package dimension design and the application design in PCB board. Polyimide, solder joint array layout with different width and length ratio and the PCB board via layout are simulated to improve the reliability performance. The models with different polyimide layouts and different material are studied in both thermal cycling and drop test. Then, the impact of different bump array width and length ratio on the next generation of the WLCSP is studied for the reliability performance. Finally, the impact of different PCB board via design and layout on the reliability performance of next generation WLCSP is analyzed in thermal cycling test. Different through board vias and blind vias array in PCB board are studied.
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