A novel study of mold compound effect towards TCoB and process integration for power leadless package

H. T. Wang, W. Tan, C. F. Cheong
{"title":"A novel study of mold compound effect towards TCoB and process integration for power leadless package","authors":"H. T. Wang, W. Tan, C. F. Cheong","doi":"10.1109/ESTC.2014.6962808","DOIUrl":null,"url":null,"abstract":"Solder joint crack in thermal cycling on board (TCoB) for surface mount devices (SMD) is becoming more stringent in semiconductor market. Current TCoB literature mainly focuses on Finite Element Analysis simulation with ANSYS software to identify the most sensitive parameters affecting TCoB performance and estimating the solder fatigue life. By a given Driver Mosfet Power QFN, this paper is focusing on actual TCoB by modifying mold compound's coefficient of thermal expansion (CTE) and storage modulus by altering the filler loading percentage and adding in additive either stress relief additive (SRA) or silicone. These modifications reduce mold compound viscosity, increase CTE1, mold shrinkage potentially increases challenges in wire sweep and map molding panel warpage. Six different mold compounds are assembled and soldered on a PCB board with TCoB condition of -40°C to 125°C. The judging criteria is concentrating on solder joint crack. Package level reliability MSL3@260°C, 500 cycle TC(-65/150°C) and 96h PCT are evaluated. Material analysis of Thermal Mechanical Analysis (TMA) and Dynamic Mechanical Analysis (DMA) are employed to analyze the coefficient of thermal expansion (CTE), glass transition temperature (Tg) and storage modulus of six different mold compounds. Filler loading reduction increase liquid to solid particles ratio, therefore wire sweep and process mapping result for all mold compounds are comparable. Increment of resin induce criticalness of panel warpage as mold shrinkage increases, result shows that filler content ≤87wt% increases panel warpage > 0.7mm which increase the difficulty in package singulation. Experimental TCoB reviews that corner leads are subjected to the highest thermal mechanical stress and becomes the initiation point of solder joint crack. Result further validates storage modulus is primary factor of mold compound instead of CTE1. Higher solder joint thickness ≥34μm is sufficient to prevent solder joint crack and meet TCoB requirement.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"18 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESTC.2014.6962808","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

Solder joint crack in thermal cycling on board (TCoB) for surface mount devices (SMD) is becoming more stringent in semiconductor market. Current TCoB literature mainly focuses on Finite Element Analysis simulation with ANSYS software to identify the most sensitive parameters affecting TCoB performance and estimating the solder fatigue life. By a given Driver Mosfet Power QFN, this paper is focusing on actual TCoB by modifying mold compound's coefficient of thermal expansion (CTE) and storage modulus by altering the filler loading percentage and adding in additive either stress relief additive (SRA) or silicone. These modifications reduce mold compound viscosity, increase CTE1, mold shrinkage potentially increases challenges in wire sweep and map molding panel warpage. Six different mold compounds are assembled and soldered on a PCB board with TCoB condition of -40°C to 125°C. The judging criteria is concentrating on solder joint crack. Package level reliability MSL3@260°C, 500 cycle TC(-65/150°C) and 96h PCT are evaluated. Material analysis of Thermal Mechanical Analysis (TMA) and Dynamic Mechanical Analysis (DMA) are employed to analyze the coefficient of thermal expansion (CTE), glass transition temperature (Tg) and storage modulus of six different mold compounds. Filler loading reduction increase liquid to solid particles ratio, therefore wire sweep and process mapping result for all mold compounds are comparable. Increment of resin induce criticalness of panel warpage as mold shrinkage increases, result shows that filler content ≤87wt% increases panel warpage > 0.7mm which increase the difficulty in package singulation. Experimental TCoB reviews that corner leads are subjected to the highest thermal mechanical stress and becomes the initiation point of solder joint crack. Result further validates storage modulus is primary factor of mold compound instead of CTE1. Higher solder joint thickness ≥34μm is sufficient to prevent solder joint crack and meet TCoB requirement.
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电源无引线封装中模具复合效应对TCoB和工艺集成的新研究
半导体市场对表面贴装器件(SMD)板上热循环(TCoB)焊点裂纹的要求越来越严格。目前的TCoB文献主要集中在利用ANSYS软件进行有限元分析仿真,以确定影响TCoB性能的最敏感参数并估计焊料疲劳寿命。在给定的驱动Mosfet功率QFN下,通过改变填充剂加载百分比和添加应力消除添加剂(SRA)或有机硅来改变模具化合物的热膨胀系数(CTE)和存储模量,从而获得实际的TCoB。这些修改降低了模具复合粘度,增加了CTE1,模具收缩潜在地增加了钢丝扫描和地图成型板翘曲的挑战。六种不同的模具化合物组装和焊接在PCB板上,TCoB条件为-40°C至125°C。判断标准主要集中在焊点裂纹上。评估了封装级可靠性MSL3@260°C, 500周期TC(-65/150°C)和96小时PCT。采用热力学分析(TMA)和动态力学分析(DMA)对六种不同模具化合物的热膨胀系数(CTE)、玻璃化转变温度(Tg)和储存模量进行了分析。填充物负荷的减少增加了液体与固体颗粒的比例,因此所有模具化合物的钢丝扫描和工艺绘图结果都是可比较的。树脂含量的增加会随着模具收缩率的增加而引起板坯翘曲临界,结果表明:填料含量≤87wt%使板坯翘曲增大> 0.7mm,增加了封装模拟的难度。TCoB实验表明,角线受到最大的热机械应力,成为焊点裂纹的起始点。结果进一步验证了储模量是模具复合材料的主要影响因素,而不是CTE1。较高的焊点厚度≥34μm足以防止焊点裂纹,满足TCoB要求。
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