Improved Blocking and Switching Characteristics of Split-Gate 1.2kV 4H-SiC MOSFET with a Deep P-well

Abstract

This paper presents the development and evaluation of a 1.2 kV 4H-SiC Split-Gate (SG) MOSFET with a deep P-well structure that effectively reduces the maximum electric field in the gate oxide (Eox), increases the short-circuit withstand time (SCWT), and reduces the switching energy loss. Channeling implantation was implemented to achieve a deep junction with low implantation energy in the proposed SG-MOSFET. The conventional MOSFET, conventional SG-MOSFET, and proposed SG-MOSFET were successfully fabricated and evaluated. The measured static, dynamic, and short-circuit characteristics were compared. In addition, 2D simulations were conducted to support the experimental results and extract the electric field in the gate oxide. The proposed SG-MOSFET outperforms the conventional SG-MOSFET with a 1.06× increase in BV and a 1.78× decrease in Eox. Additionally, the proposed SG-MOSFET shows a 1.52× improvement in SCWT compared to the conventional SG-MOSFET. Further, the proposed SG-MOSFET enhances [Ron × Crss] by 2.66× in comparison to the conventional SG-MOSFET, leading to the reduction of Eoff and Etotal by 1.5× and 1.05×, respectively.