Deep sub-micron ultra-low power CMOS device design and optimization

Abstract

In this work, CMOS devices with very low leakage current (Ioff) are studied for Ultra Low Power (ULP) applications. The ULP is targeted for worst-case Ioff <0.5 pA//spl mu/m. We used our 0.15 /spl mu/m and 0.18 /spl mu/m base line process to optimize the Vt, LDD, pocket and S/D implant to reduce device GIDL, poly edge junction leakage, band to band leakage and DIBL. A ULP product, CMOS I Mbit SRAM with measured minimum standby current < 10 /spl mu/A were fabricated successfully.