Characterization and model development of CMOS floating gate defect (FGD)

Abstract

In this paper, a structured development of model and testing strategies for floating gate defect (FGD) are described. It is shown that by using proposed testing strategies, it is possible to reduce defect escapee and easier for defect model migration to different processes. The scopes of work discussed in this paper are focused on characterisation, model development and the detectability of the FGD which usually requires careful and accurate knowledge of the process parameters, including parasitic components of the circuit. The detectability of FGD in scaled down technologies and process variation is examined as well. Simulation results proved that the new developed model is simple yet reliable in FGD detection.