{"title":"Z2-FET: Application in Image Sensing and Self-aligned Structure for Further Scaling Down","authors":"J. Liu, J. Wan","doi":"10.23919/IWJT.2019.8802620","DOIUrl":null,"url":null,"abstract":"Zero impact ionization and zero subthreshold swing FET (Z 2 -FET) based on fully depleted silicon-on-insulator (FD-SOI) substrate is a novel device operating with the positive feedback mechanism between the flow of electrons and holes. It has been showing extremely sharp-switching property with SS down to 1mV/dec and ON/OFF ratio up to 10 8 [1] , [2] . Besides, the Z 2 -FET has a large hysteresis window from its I D −V D characteristics and the turn-on voltage (V ON ) linearly controlled by the gate voltage (V G ). This property has been utilized for one-transistor dynamic random access memory (DRAM) application, which has higher access speed and higher integration density compared to conventional one-transistor and one capacitor (1T-1C) DRAM [3] , [4] . However, conventional Z 2 -FET has an asymmetrical structure with a long channel region uncovered by the top gate. This asymmetrical structure not only causes increase of feature size, but also brings mis-alignment which can degrade the device performances.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"66 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 19th International Workshop on Junction Technology (IWJT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/IWJT.2019.8802620","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Zero impact ionization and zero subthreshold swing FET (Z 2 -FET) based on fully depleted silicon-on-insulator (FD-SOI) substrate is a novel device operating with the positive feedback mechanism between the flow of electrons and holes. It has been showing extremely sharp-switching property with SS down to 1mV/dec and ON/OFF ratio up to 10 8 [1] , [2] . Besides, the Z 2 -FET has a large hysteresis window from its I D −V D characteristics and the turn-on voltage (V ON ) linearly controlled by the gate voltage (V G ). This property has been utilized for one-transistor dynamic random access memory (DRAM) application, which has higher access speed and higher integration density compared to conventional one-transistor and one capacitor (1T-1C) DRAM [3] , [4] . However, conventional Z 2 -FET has an asymmetrical structure with a long channel region uncovered by the top gate. This asymmetrical structure not only causes increase of feature size, but also brings mis-alignment which can degrade the device performances.