Improving a design methodology of synthesizable VHDL with formal verification

Abstract

In this paper we present a synthesizable VHDL design methodology that includes exhaustive verification of properties. The work was developed in a company environment with the goal of increasing reliability of products and reduce time of verification procedure. In this methodology the properties are represented using VHDL oriented patterns based on the OVL library and applied, with the VHDL code, into a verification environment (based on open source tools) that returns the results. Counterexamples are generated for properties that failed and returned as VHDL testbench, allowing the user to identify the faulty behavior with simulation. The methodology is illustrated with a simple memory controller application.