Parasitic source/drain resistance reduction in n-channel SOI MuGFETs with 15nm wide fins

Abstract

We report on a set of process improvements leading to parasitic S/D resistance reduction in n-channel MuGFETs with 60 nm tall and 15 nm wide fins. We experimentally determine the contributions to the parasitic S/D resistance arising from the specific regions of the S/D geometry. A 50% reduction in the S/D resistance (from 1235 to 600 /spl Omega/-/spl mu/m) is achieved by introducing various scaled processes, including EOT reduction, elevated S/D, undoped fins and removal of halos, reduction in S/D spacer width, and smaller gate lengths. The combination of these process enhancements leads to a 2/spl times/ increase in I/sub DSAT/, measured at constant I/sub OFF/ (=1nA//spl mu/m) and V/sub DD/=1.3V.